Substrate noise isolation experiments in a 0.18 μm 1P6M triple-well CMOS process on a lightly doped substrate

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn , Issue , 2007, Pages

  Vinella, R M ^a,b   Van Der Plas, G ^b   Soens, C ^b   Rizzi, M ^a   Castagnolo, B ^a  

^a POLITECNICO DI BARI   (Italy)

^b IMEC   (Belgium)

Author keywords

Guarding structures grounding; Noise isolation

Indexed keywords

DOPING (ADDITIVES); MAGNETIC COUPLINGS; SPURIOUS SIGNAL NOISE; SUBSTRATES; TOPOLOGY;

AGGRESSORS; GUARDING STRUCTURES GROUNDING; NOISE ISOLATION;

CMOS INTEGRATED CIRCUITS;

EID: 34648819369     PISSN: 10915281     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/imtc.2007.379286     Document Type: Conference Paper

References (5)

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5. D. Kosaka, M. Nagata, "Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation", in Proc. Asia and South Pacific Conference on Design Automation 2006, pp.677-682