A 250mW full-rate 10Gb/s transceiver core in 90nm CMOS using a tri-state binary PD with 100ps gated digital output

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 438-440

  Masuda, Takashi ^a   Suzuki, Hideyuki ^a   Iizuka, Hiroshi ^a   Igarashi, Akiko ^a   Takeshita, Kaneyoshi ^a   Mogi, Takayuki ^a   Shoji, Norio ^a,b   Chatwin, Jeremy ^b   Butler, Iain ^b   Mellor, Derek ^b  

^a SONY CORPORATION   (Japan)

^b Mixed Signal Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FREQUENCY MODULATION; GATES (TRANSISTOR); VARIABLE FREQUENCY OSCILLATORS;

GATED DIGITAL OUTPUT; INPUT SENSITIVITY; TRI-STATE BINARY PD;

TRANSCEIVERS;

EID: 34548824364     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373482     Document Type: Conference Paper

References (7)

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