Ultra low voltage design considerations of soi sram memory cells

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4094-4097

  Thomas, Olivier ^a   Amara, Amara ^a  

^a ISEP   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL DESIGN METHODS; FLOATING BODY TRANSISTORS; PARTIALLY DEPLETED SOI; SOI TECHNOLOGY; SRAM CELL; SRAM MEMORY CELLS; SYSTEMATIC DESIGNS; ULTRA-LOW-VOLTAGE;

MOSFET DEVICES; SEMICONDUCTOR STORAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 33646154483     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465531     Document Type: Conference Paper

References (11)

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9. E. Seevinck, F. J. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, October 1987.
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