Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro devices

Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI)

Volumn P-81, Issue , 2006, Pages 122-131

  Claus, Christopher ^a   Muller, Florian Helmut ^a   Stechele, Walter ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

BITSTREAMS; DYNAMIC AND PARTIAL RECONFIGURATION; FIELD PROGRAMMABLES; NEW APPROACHES; PARTIAL DYNAMIC RECONFIGURATION; PROGRAMMABLE GATE ARRAY; RECONFIGURABLE; RECONFIGURATION TIME; RUNTIMES; SYSTEMS-ON-CHIP;

SYSTEM-ON-CHIP;

EID: 34548368191     PISSN: 16175468     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. S. A. Guccione, D. Levi und P. Sundarajan. JBits: Java based interface for reconfigurable computing. Proceedings of2ndAnnual Military andAerospace Applicationsfor Programmable Devices and Technologies, September 1999.
4. A. K. Raghavan und P. Sutton. JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS.02), 2002.
5. W. Stechele, L. Alvado Carcel, S. Herrmann und J. Lidon Simon. A Coprocessor for Accelerating Visual Information Processing. DATE, 2005.
6. Xilinx. Two flows for Partial Reconfiguartion: Module based or Difference Based. Application Note XAPP290 (v 1.2), September 2004.
7. Xilinx. Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 (v.4.0), Seiten 337-365, March 2005.
8. Xilinx. Development System Reference Guide, Seiten 75-113, 2005.