Novel architecture for two-dimensional high throughput rate real-time discrete cosine transform and the VLSI design

International Journal of Electronics

Volumn 83, Issue 4, 1997, Pages 519-528

  Chiang, Jen Shiun ^a   Huang, Hsiang Chou ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 3342910503     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072197135328     Document Type: Article

References (7)

1. Ahmed, N., Natarajan, T, and Rao, K. R., 1974, Discrete cosine transform. IEEE Transactions on Computers, 23, 90-93.
2. Balir, G. M., 1992, PLA design for single-clock CMOS. IEEE Journal Solid-state Circuits, 27, 1211-1213.
3. Carlach, J. C., Penard, P., Sicre, J. L., 1989, Sicre, TCAD: a 27MHz 8 x 8 discrete cosine transform chip. Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP’89), pp. 2429-2432.
4. Kim, S. P., and Pan, D. K.,1992, Highly modular and concurrent 2-D DCT chip. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1081-1084.
5. Sheu, M. H., Lee, J. Y, Wang, J. F., Suen, A. N., and Liu, L. Y, 1993, A high throughput-rate architecture for 8 x 8 2-D DCT. Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP’93), pp. 1587-1590.
6. Sjostrom, U., Defilipps, I., Ansorge, M., and Pellandini, F., 1990, Discrete cosine transform chip for real-time video application. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1620-1623.
7. Sun, M.T, Wu, L., and Liou, M. L., 1987, A concurrent architecture for VLSI implementation of discrete cosine transform. IEEE Transactions on Circuits and Systems, 34(8), 992-994.