-
1
-
-
33748423201
-
-
Atmel Corp
-
Atmel Corp. 2005. FPSLIC (AVR with FPGA), http://www.atmel.com/ products/FPSLIC/.
-
(2005)
FPSLIC (AVR with FPGA)
-
-
-
3
-
-
34548346512
-
-
Celoxica. http://www.celoxica.com.
-
-
-
Celoxica1
-
5
-
-
0036911921
-
Managing power and performance for System-on-Chip designs using Voltage Islands
-
ICCAD
-
Cohn, J.M., D.W. Stout, P.S. Zuchowski, S.W. Gould, T.R. Bednar, and D.E. Lackey. Managing power and performance for System-on-Chip designs using Voltage Islands. Int. Conf. on Computer-Aided Design (ICCAD), 2002, pp. 195-202.
-
(2002)
Int. Conf. on Computer-Aided Design
, pp. 195-202
-
-
Cohn, J.M.1
Stout, D.W.2
Zuchowski, P.S.3
Gould, S.W.4
Bednar, T.R.5
Lackey, D.E.6
-
7
-
-
34548333218
-
-
Critical Blue. 2005. http://www.criticalblue.com
-
(2005)
Critical Blue
-
-
-
8
-
-
0030784055
-
-
Eles, P., Z. Peng, K. Kuchcinsky, and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Design Automation for Embedded Systems, vol2, no 1, 5-32 Jan. 1997
-
Eles, P., Z. Peng, K. Kuchcinsky, and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Design Automation for Embedded Systems, vol2, no 1, 5-32 Jan. 1997
-
-
-
-
10
-
-
0001858873
-
Hardware-Software Cosynthesis For Digital Systems
-
September
-
Gupta, R. and G. De Micheli. Hardware-Software Cosynthesis For Digital Systems. IEEE Design and Test of Computers. Pages 29-41, September 1993
-
(1993)
IEEE Design and Test of Computers
, pp. 29-41
-
-
Gupta, R.1
De Micheli, G.2
-
11
-
-
16244400467
-
Architecting Voltage Islands in Core-Based System-on-a-Chip Designs
-
Hu, J., Y. Shin, N. Dhanwada, and R. Marculescu. Architecting Voltage Islands in Core-Based System-on-a-Chip Designs. Int. Symp. on Low Power Electronics and Design (ISLPED), 2004, pp. 180-185.
-
(2004)
Int. Symp. on Low Power Electronics and Design (ISLPED)
, pp. 180-185
-
-
Hu, J.1
Shin, Y.2
Dhanwada, N.3
Marculescu, R.4
-
13
-
-
33845594450
-
-
Keogh, E.J., S. Chu, D. Hart, and M.J. Passani. An Online Algorithm for Segmenting Time Series. IEEE Int. Conf. on Data Mining, pp. 289-296, 2001
-
(2001)
An Online Algorithm for Segmenting Time Series. IEEE Int. Conf. on Data Mining
, pp. 289-296
-
-
Keogh, E.J.1
Chu, S.2
Hart, D.3
Passani, M.J.4
-
14
-
-
84944403811
-
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
-
Kumar, R., K.I. Farkas, N.P. Jouppi, P. Ranganathan, and D.M. Tullsen. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. Int. Symposium on Microarchitecture (MICRO), 2003.
-
(2003)
Int. Symposium on Microarchitecture (MICRO)
-
-
Kumar, R.1
Farkas, K.I.2
Jouppi, N.P.3
Ranganathan, P.4
Tullsen, D.M.5
-
15
-
-
84943178465
-
Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-Chip Systems. IEEE Int
-
Muttersbach, J., T Villiger, H Kaeslin, N Felber, and W. Fichtner. Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-Chip Systems. IEEE Int. ASIC/SOC Conference, 1999.
-
(1999)
ASIC/SOC Conference
-
-
Muttersbach, J.1
Villiger, T.2
Kaeslin, H.3
Felber, N.4
Fichtner, W.5
-
16
-
-
34548351387
-
-
Mimosys. http://http://www.mimosys.com/.
-
-
-
Mimosys1
http2
-
17
-
-
84942851882
-
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
-
Miyamori, T., and U. Olukotun. A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. FPGAs for Custom Computing Machines (FCCM). 1998, pp. 2-11.
-
(1998)
FPGAs for Custom Computing Machines (FCCM)
, pp. 2-11
-
-
Miyamori, T.1
Olukotun, U.2
-
18
-
-
0000819568
-
The Number of Partitions of a Set
-
Rota, Gian Carlo. The Number of Partitions of a Set. American Mathematical Monthly., Vol 71. No 5 pp 498-504. 1964.
-
(1964)
American Mathematical Monthly
, vol.71
, Issue.5
, pp. 498-504
-
-
Rota, G.C.1
-
19
-
-
0345272496
-
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
-
Semeraro, G., G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M.L. Scott. Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. Int. Symp. on High-Performance Computer Architecture (HPCA), 2002.
-
(2002)
Int. Symp. on High-Performance Computer Architecture (HPCA)
-
-
Semeraro, G.1
Magklis, G.2
Balasubramonian, R.3
Albonesi, D.H.4
Dwarkadas, S.5
Scott, M.L.6
-
20
-
-
85013441915
-
Energy Savings and Speedups From Partitioning Critical Software Loops to Hardware in Embedded Systems
-
January
-
Stitt, G., F. Vahid, and S. Nematbakshi. Energy Savings and Speedups From Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004.
-
(2004)
IEEE Transactions on Embedded Computer Systems
-
-
Stitt, G.1
Vahid, F.2
Nematbakshi, S.3
-
21
-
-
27644517741
-
Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode
-
CODES/ISSS, Sep
-
Stitt, G., F. Vahid, G. McGregor, B. Einloth Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode. Int. Conf. on Hardware/Software Codesign and System Synthesis (CODES/ISSS), Sep. 2005.
-
(2005)
Int. Conf. on Hardware/Software Codesign and System Synthesis
-
-
Stitt, G.1
Vahid, F.2
McGregor, G.3
Einloth, B.4
-
23
-
-
84976701936
-
Limits of instruction-level parallelism
-
April
-
Wall, D. Limits of instruction-level parallelism. ACM SIGARCH Computer Architecture News. Volume 19 , Issue 2, pp. 176-188 April 1991.
-
(1991)
ACM SIGARCH Computer Architecture News
, vol.19
, Issue.2
, pp. 176-188
-
-
Wall, D.1
|