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Volumn , Issue , 2007, Pages 397-402

Clock-frequency assignment for multiple clock domain systems-on-a-chip

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CIRCUIT SIMULATION; DYNAMIC PROGRAMMING; PROBLEM SOLVING; TIME AND MOTION STUDY;

EID: 34548348869     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364624     Document Type: Conference Paper
Times cited : (5)

References (24)
  • 1
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    • Atmel Corp
    • Atmel Corp. 2005. FPSLIC (AVR with FPGA), http://www.atmel.com/ products/FPSLIC/.
    • (2005) FPSLIC (AVR with FPGA)
  • 3
    • 34548346512 scopus 로고    scopus 로고
    • Celoxica. http://www.celoxica.com.
    • Celoxica1
  • 7
    • 34548333218 scopus 로고    scopus 로고
    • Critical Blue. 2005. http://www.criticalblue.com
    • (2005) Critical Blue
  • 8
    • 0030784055 scopus 로고    scopus 로고
    • Eles, P., Z. Peng, K. Kuchcinsky, and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Design Automation for Embedded Systems, vol2, no 1, 5-32 Jan. 1997
    • Eles, P., Z. Peng, K. Kuchcinsky, and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Design Automation for Embedded Systems, vol2, no 1, 5-32 Jan. 1997
  • 10
    • 0001858873 scopus 로고
    • Hardware-Software Cosynthesis For Digital Systems
    • September
    • Gupta, R. and G. De Micheli. Hardware-Software Cosynthesis For Digital Systems. IEEE Design and Test of Computers. Pages 29-41, September 1993
    • (1993) IEEE Design and Test of Computers , pp. 29-41
    • Gupta, R.1    De Micheli, G.2
  • 15
    • 84943178465 scopus 로고    scopus 로고
    • Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-Chip Systems. IEEE Int
    • Muttersbach, J., T Villiger, H Kaeslin, N Felber, and W. Fichtner. Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-Chip Systems. IEEE Int. ASIC/SOC Conference, 1999.
    • (1999) ASIC/SOC Conference
    • Muttersbach, J.1    Villiger, T.2    Kaeslin, H.3    Felber, N.4    Fichtner, W.5
  • 16
    • 34548351387 scopus 로고    scopus 로고
    • Mimosys. http://http://www.mimosys.com/.
    • Mimosys1    http2
  • 17
    • 84942851882 scopus 로고    scopus 로고
    • A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
    • Miyamori, T., and U. Olukotun. A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. FPGAs for Custom Computing Machines (FCCM). 1998, pp. 2-11.
    • (1998) FPGAs for Custom Computing Machines (FCCM) , pp. 2-11
    • Miyamori, T.1    Olukotun, U.2
  • 18
    • 0000819568 scopus 로고
    • The Number of Partitions of a Set
    • Rota, Gian Carlo. The Number of Partitions of a Set. American Mathematical Monthly., Vol 71. No 5 pp 498-504. 1964.
    • (1964) American Mathematical Monthly , vol.71 , Issue.5 , pp. 498-504
    • Rota, G.C.1
  • 20
    • 85013441915 scopus 로고    scopus 로고
    • Energy Savings and Speedups From Partitioning Critical Software Loops to Hardware in Embedded Systems
    • January
    • Stitt, G., F. Vahid, and S. Nematbakshi. Energy Savings and Speedups From Partitioning Critical Software Loops to Hardware in Embedded Systems. IEEE Transactions on Embedded Computer Systems, January 2004.
    • (2004) IEEE Transactions on Embedded Computer Systems
    • Stitt, G.1    Vahid, F.2    Nematbakshi, S.3
  • 23
    • 84976701936 scopus 로고
    • Limits of instruction-level parallelism
    • April
    • Wall, D. Limits of instruction-level parallelism. ACM SIGARCH Computer Architecture News. Volume 19 , Issue 2, pp. 176-188 April 1991.
    • (1991) ACM SIGARCH Computer Architecture News , vol.19 , Issue.2 , pp. 176-188
    • Wall, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.