Increasing pipelined IP core utilization in process networks using exploration

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 690-699

  Zissulescu, Claudiu ^a   Kienhuis, Bart ^a   Deprettere, Ed ^a  

^a LEIDEN UNIVERSITY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE; MATLAB; RECONFIGURABLE HARDWARE;

DATA PATHS; HARDWARE IMPLEMENTATIONS; IN-PROCESS; IP CORE; PROCESS NETWORKS; QR ALGORITHMS; RECONFIGURABLE PLAT-FORMS; RESEARCH CENTER;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548326425     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_70     Document Type: Article

References (12)

1. A. Bakshi, V. K. Prasanna, and A. Ledeczi. Milan: A model based integrated simulation framework for design of embedded systems. In ACM SIGPLAN workshop, 2001.
2. U. K. Banerjee. Loop Transformations for Restructuring Compilers: The Foundations. Kluwer Academic Publishers, 1993.
3. S. Derrien and S. Rajoupadyhe. Loop tiling for reconfigurable accelerators. In FPL 2001, UK, 2001.
4. E. Ehrhart. Polynômes arithmétiques et Méthode des Polyédres en Combinatoire. Birkhäuser Verlag, Basel, international series of numerical mathematics vol. 35 edition, 1977.
5. V. Kathail, S. Aditya, R. Schreiber, B. R. Rau, D. C. Cronquist, and M. Sivaraman. Pico: Automatically designing custom computers. Computer, 35(9):39-47, 2002.
6. B. Kienhuis, E. Rypkema, and E. Deprettere. Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures. In CODES, San Diego, USA 2000.
7. C. Leiserson and J. Saxe. Optimizing synchronous systems. Journal of VLSI and Computer Systems, 1, 1983.
8. K. S. Shayee, J. Park, and P. Diniz. Performance and area modeling of complete fpga designs in the presence of loop transformations. In FPL 2003, Portugal, 2003.
9. T. Stefanov, B. Kienhuis, and E. Deprettere. Algorithmic transformation techniques for efficient exploration of alternative application instances. In CODES'02, USA 2002.
10. T. Stefanov, C. Zissulescu, A. Turjan, B. Kienhuis, and E. Deprettere. System design using kahn process networks: The compaan/laura approach. In DATE2004, Paris, France, 2004.
11. R. Walke and R. Smith. 20 gflops qr processor on a xilinx virtex-e fpga. In Advanced Signal Processing Algorithms, Architectures, and Implementations X, volume 4116, 2000.
12. C. Zissulescu, T. Stefanov, B. Kienhuis, and E. Deprettere. LAURA: Leiden Architecture Research and Exploration Tool. In FPL'03, Portugal, 2003.