Performance and area modeling of complete FPGA designs in the presence of loop transformations

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 296-

  Shayee, K R S ^a   Park, Joonseok ^b   Diniz, P C ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Bandwidth; Computer languages; Delay; Field programmable gate arrays; Hardware; Image processing; Information analysis; Parallel processing; Performance analysis; Read write memory

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; BANDWIDTH; COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; COMPUTERS; HIGH LEVEL LANGUAGES; IMAGE MATCHING; IMAGE PROCESSING; INFORMATION ANALYSIS; MEMORY ARCHITECTURE; PIPELINE PROCESSING SYSTEMS; PRIVATIZATION;

DELAY; FINE GRAIN PARALLELISM; FPGA-BASED ARCHITECTURES; HIGH-LEVEL PROGRAMMING LANGUAGE; IMAGE PROCESSING ALGORITHM; PARALLEL PROCESSING; PERFORMANCE ANALYSIS; PROGRAM TRANSFORMATIONS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84942870302     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227278     Document Type: Conference Paper

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