VLSI design of a high-speed and area-efficient JPEG2000 encoder

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 17, Issue 8, 2007, Pages 1065-1078

  Mei, Kuizhi ^b   Zheng, Nanning ^a,b   Huang, Chang ^b   Liu, Yuehu ^b   Zeng, Qiang ^c  

^a IEEE

^b XI'AN JIAOTONG UNIVERSITY   (China)

^c Viatech Corporation   (China)

Author keywords

Arithmetic encoder, bit plane encoder (BPE); Discrete wavelet transform (DWT); Field programmable gate array (FPGA); JPEG2000 encoder; Tier2; VLSI

Indexed keywords

BUFFER CIRCUITS; DATA COMPRESSION; DISCRETE WAVELET TRANSFORMS; ENCODING (SYMBOLS); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT LAYOUT;

ARITHMETIC ENCODERS; BIT PLANE ENCODER (BPE); JPEG2000 ENCODERS;

VLSI CIRCUITS;

EID: 34548239138     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2007.903555     Document Type: Article

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