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Volumn 2, Issue , 2004, Pages
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High speed VLSI architecture for bit plane encoder of JPEG2000
a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
BOUNDARY CONDITIONS;
ENCODING (SYMBOLS);
FIELD PROGRAMMABLE GATE ARRAYS;
SAMPLING;
WAVELET TRANSFORMS;
BIT PLANE ENCODER;
HARDWARE COST;
IMAGE STATISTICS;
SAMPLE LOCATION;
VLSI CIRCUITS;
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EID: 11144251696
PISSN: 15483746
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (26)
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References (6)
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