Efficient VLSI architecture for buffer used in EBCOT Of JPEG2000 encoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4361-4364

  Gupta, Amit Kumar ^a   Nooshabadi, Saeid ^a   Taubman, David ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ACCEPTING CAPACITY; BLOCK CODERS; BUFFER LENGTH; BUFFER PARAMETERS; CONCURRENT SYMBOL PROCESSING; EBCOT BLOCK CODER; HARDWARE COST; JPEG 2000; JPEG2000 ENCODER; LOW COSTS; NATURAL IMAGES; OPTIMAL SELECTION; VLSI ARCHITECTURES;

COMPUTER OPERATING PROCEDURES; THROUGHPUT;

DIGITAL IMAGE STORAGE;

EID: 34547299863     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465597     Document Type: Conference Paper

References (8)

1. JPEG2000 Part I Final Committee Draft Version 1.0, ISO/IEC JTC1/SC29/WG1 N1646R, Mar. 2000.
2. D. Taubman, "High Performance scalable image compression with EBCOT," IEEE Trans. Image Processing, vol. 9, pp. 1158-1170, July 2000.
3. D. S. Taubman and M. W. Marcellin, JPEG 2000: Image Compression, Fundamentals, Standards and Practice. Norwell, MA:Kluwer, 2002.
4. Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen, Liang-Gee Chen, "Analysis and architecture design of block-coding engine for EBCOT in JPEG2000," in IEEE Tran. Circuits and Systems for Video Technology, vol. 13, pp. 219-230, March 2003.
5. Kishore Andra, Tinku Acharya, Chaitali Chakrabarti, "Efficient VLSI implementation of Bit Plane Coder of JPEG2000," in Proc. SPIE Int. Conf. Applications of Digital Image Processing XXIV, vol. 4472, pp. 246-257.
6. Amit Kr. Gupta, D. Taubman, S. Nooshabadi, "High speed parallel pipeline architecture for Bit Plane Coder of JPEG2000 encoder," accepted in IEEE MWSCAS, 2004.
7. M. Dyer, D. Taubman, S. Nooshabadi, "Improved throughput arithmetic coder for JPEG2000," accepted in IEEE Int. Conf. Image Processing, 2004.
8. Y. Tamir and G.L. Frazier, "High-performance multiqueue buffers for VLSI communication switches," in Symp. IEEE International Conference on Computer Architecture, pp. 343-354, June 1988.