Designing for high product yield

Semiconductor International

Volumn 25, Issue 12, 2002, Pages 83-88

  Ciplickas, Dennis ^a   Joshi, Aniruddha ^a   Lee, Sherry F ^a   Strojwas, Andrzej J ^a  

^a PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECT DENSITY; DEFECT SIZE DISTRIBUTION (DSD); RANDOM DEFECTS; YIELD IMPACT;

COSTS; FOUNDRY PRACTICE; MARKETING; MICROPROCESSOR CHIPS; OPTIMIZATION; POLYSILICON; PROBABILITY; RANDOM PROCESSES; ROUTERS; SEMICONDUCTOR DEVICE MANUFACTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 3142621461     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (1)

1. D.J. Ciplickas, X. Li, A.J. Strojwas, "Predictive Yield Modeling of VLSICs," Proc. of IWSM 2000, Honolulu, June 2000.