Parametric testing of HYPRES superconducting integrated circuit fabrication processes

IEEE Transactions on Applied Superconductivity

Volumn 17, Issue 2, 2007, Pages 181-186

  Yohannes, Daniel ^a   Kirichenko, Alex ^a   Sarwana, Saad ^a   Tolpygo, Sergey K ^a  

^a HYPRES INC   (United States)

Author keywords

Critical current; Josephson device fabrication; Josephson junction; Sheet inductance; Sheet resistance; Statistical process control; Superconducting integrated circuits

Indexed keywords

ALGORITHMS; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); DIGITAL CIRCUITS; JOSEPHSON JUNCTION DEVICES; PARAMETER ESTIMATION; SHEET RESISTANCE; STATISTICAL PROCESS CONTROL;

DIAGNOSTIC CHIPS; DIAGNOSTIC STRUCTURES; SHEET INDUCTANCE; SUPERCONDUCTING INTEGRATED CIRCUITS;

INTEGRATED CIRCUITS;

EID: 34547425412     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2007.897399     Document Type: Conference Paper

References (16)

1. O. A. Mukhanov, D. Gupta, A. Kadin, and V. K. Semenov, "Superconductor analog-to-digital converters," Proc. IEEE, vol. 92, no. 10, pp. 1564-1584, Oct. 2004.
2. D. Gupta, T. V. Filippov, A. F. Kirichenko, D. E. Kirichenko, I. V. Vernik, A. Sahu, S. Sarwana, P. Shevchenko, A. Talalaevskii, and O. A. Mukhanov, "Digital channelizing radio frequency receiver," IEEE Trans. Appl. Supercond., ASC2006 paper 2EX01, submitted for publication.
3. I. V. Vernik, D. E. Kirichenko, T. V. Filippov, A. Talalaevskii, A. Sahu, A. Inamdar, A. F. Kirichenko, D. Gupta, and O. A. Mukhanov, "Superconducting high-resolution, low pass analog-to-digital converters," IEEE. Trans. Appl. Supercond., ASC2006 paper 2EX04, submitted for publication.
4. L. A. Abelson, S. L. Thomasson, J. M. Murduck, R. Elmadjian, G. Akerling, R. Kono, and H. W. Chan, "A superconductive integrated circuit foundry," IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 2043-2049, Mar. 1993.
5. L. A. Abelson and G. L. Kerber, "Superconductor integrated circuit fabrication technology," Proc. IEEE, vol. 92, no. 10, pp. 1517-1533, Oct. 2004.
6. I. Ishida, S. Tahara, M. Hidaka, S. Nagasawa, S. Tuschida, and Y. Wada, "A fabrication process for a 580 ps 4 kbit Josephson nondestructive read-out RAM," IEEE Trans. Magn., vol. 7, pp. 313-316, Mar. 1991.
7. L. Abelson, K. Daly, N. Martinez, and A. D. Smith, "LTS Josephson critical current densities for LSI applications," IEEE Trans. Appl. Supercond., vol. 5, pp. 2727-2730, Jun. 1995.
8. J. E. Savageau, J. Burroughs, P. A. A. Booi, M. W. Cromar, S. P. Benz, and J. A. Koch, "Superconducting integrated circuit fabrication with low temperature ECR-based PECVD SiO2 dielectric films," IEEE Trans. Appl. Supercond., vol. 5, pp. 2303-2309, Jun. 2005.
9. L. W. Linholm, R. A. Allen, and M. W. Cresswell, "Microelectronic test structures for feature placement and electrical linewidth metrology," in Handbook of Critical Dimension Metrology and Process Control, K. M. Mohan, Ed. Bellingham, WA: SPIE Press, 1993.
10. E. G. Colgan, R. J. Polastre, M. Takeichi, and R. L. Wisnieff, "Thin-film-transistor process-characterization test structures," IBM J. Res. Dev., vol. 42, no. 3/4, pp. 481-490, 1998.
11. 2 Nb/AlOx/Nb fabrication processes," IEEE Trans. Appl. Supercond., vol. 15, pp. 90-93, 2005.
12. 2 process development for superconductor integrated circuits with 80 GHz clock, frequency," IEEE Trans. Appl. Supercond., ASC2006 paper 3EA01, submitted for publication.
13. "Design rules, Niobium integrated circuits fabrication," Process #03-10-45 [Online]. Available: www.hypres.com (follow link to Foundry)
14. A. W. Kleinsasser, M. W. Johnson, and K. A. Delin, "Direct measurement of the Josephson plasma resonance frequency from I-V characteristics," IEEE Trans. Appl. Supercond., vol. 15, pp. 86-89, 2005.
15. L. J. Van der Pauw, "A method of measuring specific resistivity and Hall effect of discs and arbitrary shapes," Philips Res. Reps., vol. 13, pp. 1-9, 1958.
16. T. V. Filippov, private communication.