Portable execution time analysis method

Proceedings - 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2006

Volumn , Issue , 2006, Pages 267-270

  Yamamoto, Keiji ^a   Ishikawa, Yutaka ^a   Matsui, Toshihiro ^b  

^a UNIVERSITY OF TOKYO   (Japan)

^b NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; COMPUTER SIMULATION; PROGRAM COMPILERS; SUPERVISORY AND EXECUTIVE PROGRAMS; TIME SERIES ANALYSIS;

PORTABLE EXECUTION TIME ANALYSIS; REAL MACHINES;

STORAGE ALLOCATION (COMPUTER);

EID: 34547312124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.2006.49     Document Type: Conference Paper

References (11)

1. A. Colin and I. Puaut. Worst Case Execution Time Analysis for a Processor with Branch Prediction. Real-Time Syst., 18(2-3):249-274, 2000.
2. Intel Corporation. IA-32 Architecture Software Developer's Manual, 2004.
3. Intel Corporation. Intel XScale Core Developer's Manual, 2004.
4. S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, S.-M. Moon, and C. S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593-604, 1995.
5. M. Lindgren, H. Hansson, and H. Thane. Using Measurements to Derive the Worst-Case Execution Time. In Proc. 7th International Conference on Real-Time Computing Systems and Applications, page 15, 2000.
6. T. Lundqvist and P. Stenström. An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. Real-Time Syst., 17(2-3): 183-207, 1999.
7. G. Ottosson and M. Sjödin. Worst-Case Execution Time Analysis for Modern Hardware Architectures. In ACM SIGPLAN 1997 Workshop on Languages, Compilers, and Tools for Real-Time Systems (LCT-RTS'97), 1997.
8. S. Petters and G. Farber. Making Worst Case Execution Time Analysis for Hard Real-Time Tasks on State of the Art Processors Feasible. In Proc. 6th International Conference on Real-Time Computing Systems and Applications, 1999.
9. J. Schneider and C. Ferdinand. Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation. In LCTES '99: Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems, pages 35-44, 1999.
10. F. Stappert and P. Altenbernd. Complete Worst-Case Execution Time Analysis of Straight-line Hard Real-time Programs. J. Syst. Archit., 46(4):339-355, 2000.
11. R. T. White, C. A. Healy, D. B. Whalley, F. Mueller, and M. G. Harmon. Timing Analysis for Data Caches and Set-Associative Caches. In RTAS '97: Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97), page 192, 1997.