Pipeline behavior prediction for superscalar processors by abstract interpretation

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn Part F129197, Issue , 1999, Pages 35-44

  Schneider, Jörn ^a   Ferdinand, Christian ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; EMBEDDED SYSTEMS; FORECASTING; INTERACTIVE COMPUTER SYSTEMS; PIPELINE PROCESSING SYSTEMS; PIPELINES; PROGRAM COMPILERS; PROGRAM PROCESSORS;

ABSTRACT INTERPRETATIONS; ARCHITECTURAL COMPONENTS; BEHAVIOR PREDICTION; HARD REAL-TIME SYSTEMS; MODERN PROCESSORS; PROTOTYPICAL IMPLEMENTATION; SUPERSCALAR PROCESSOR; WORST-CASE EXECUTION TIME;

REAL TIME SYSTEMS;

EID: 33747258257     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/314403.314432     Document Type: Conference Paper

References (20)

1. T. Ball and J. Larus. Optimally Profiling and Tracing Programs. In Proceedings of the 19th ACM Symposium on Principles of Programming Languages, pages 59-70, Jan. 1992.
2. D. G. Bradlee. Retargetable Instruction Scheduling for Pipelined Processors. PhD Thesis, Technical Report 91-08-07, University of Washington, 1991.
3. P. Cousot and R. Cousot. Abstract Interpretation: A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints. In Proceedings of the 4th A CM Symposium on Principles of Programming Languages, pages 238-252, Los Angeles, CA, 1977.
4. C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. Dissertation, Universitat des Saarlandes, Sept. 1997.
5. C. Ferdinand, F. Martin, and R. Wilhelm. Applying Compiler Techniques to Cache Behavior Prediction. In Proceedings of the ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, pages 37-46, June 1997.
6. C. Ferdinand and R. Wilhelm. On predicting data cache behavior for real-time systems. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, volume 1474 of Lecture Notes in Computer Science, pages 16-30. Springer, 1998.
7. C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the Timing Analysis of Pipelining and Instruction Caching. In Proceedings of the IEEE Real-Time Systems Symposium, pages 288-297, Dec. 1995.
8. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., 2 edition, 1996.
9. Y. Hur, Y. H. Bea, S.-S. Lira, B.-D. Rhee, S. L. Min, Y. C. Park, M. Lee, H. Shin, and C. S. Kim. Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study. In Proceedings of the IEEE Real-Time Systems Symposium, pages 308-319, Dec. 1995.
10. Y.-T. S. Li, S. Malik, and A. Wolfe. Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. In Proceedings of the IEEE Real-Time Systems Symposium, pages 298-307, Dec. 1995.
11. S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, S.-M. Moon, and C. S. Kim. An Accurate Worst Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593-604, July 1995.
12. S.-S. Lim, J. H. Han, J. Kim, and S. L. Min. A worst case timing analysis technique for multiple-issue machines. In Proceedings of the IEEE Real-Time Systems Symposium'98, 1998.
13. T. Lundqvist and P. Stenström. Integrating path and timing analysis using instruction-level simulation techniques. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, volume 1474 of Lecture Notes in Computer Science, pages 1-15. Springer, 1998.
14. F. Martin. PAG - an efficient program analyzer generator. International Journal on Software Tools for Technology Transfer, 2(1):46-67, 1998.
15. F. Martin, M. Alt, R. Wilhelm, and C. Ferdinand. Analysis of Loops. In Proceedings of the 7th International Conference on Compiler Construction, volume 1383 of Lecture Notes in Computer Science. Springer, March/April 1998.
16. K. Narasimham and K. D. Nilsen. Portable Execution Time Analysis for RISC Processors. In Proceedings of the ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, 1994.
17. G. Ottoson and M. Sjodin. Worst-Case Execution Time Analysis for Modern Hardware Architectures. In Proceedings of the ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, pages 47-55, June 1997.
18. J. Schneider. Statische Pipeline-Analyse für Echtzeit-systeme. Diplomarbeit, Universität des Saarlandes, Oct. 1998.
19. SPARC International, Inc., Menlo Park California, U. S. A. The SPARC Architecture Manual, Version 8, 1992.
20. H. Theiling and C. Ferdinand. Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis. In Proceedings of the IEEE Real-Time Systems Symposium'98, pages 144-153, Dec. 1998.