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Volumn , Issue , 2006, Pages 1587-1590

Integrating observability don't cares in all-solution SAT solvers

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; ITERATIVE METHODS; NETWORKS (CIRCUITS); OPTIMIZATION; PROBLEM SOLVING; SCHEMATIC DIAGRAMS;

EID: 34547276733     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 3
    • 0026623575 scopus 로고
    • Test pattern generation using Boolean satisfiability
    • T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. on CAD, vol. 11, pp. 4-15, 1992.
    • (1992) IEEE Trans. on CAD , vol.11 , pp. 4-15
    • Larrabee, T.1
  • 4
    • 70350777567 scopus 로고    scopus 로고
    • Applying SAT methods in unbounded symbolic model checking
    • K. McMillan, "Applying SAT methods in unbounded symbolic model checking." in Computer Aided Verification, 2002, pp. 250-264.
    • (2002) Computer Aided Verification , pp. 250-264
    • McMillan, K.1
  • 6
    • 33646941314 scopus 로고    scopus 로고
    • SAT-based complete don't-care computation for network optimization
    • A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization," in Design, Automation and Test in Europe, 2005, pp. 418-423.
    • (2005) Design, Automation and Test in Europe , pp. 418-423
    • Mishchenko, A.1    Brayton, R.2
  • 7
    • 16244414873 scopus 로고    scopus 로고
    • Efficient SAT-based symbolic unbounded model checking using circuit cofactoring
    • Nov
    • M. Ganai, A. Gupta, and P. Ashar, "Efficient SAT-based symbolic unbounded model checking using circuit cofactoring," in Int'l Conf. on CAD, Nov. 2004, pp. 510-517.
    • (2004) Int'l Conf. on CAD , pp. 510-517
    • Ganai, M.1    Gupta, A.2    Ashar, P.3
  • 8
    • 13144268611 scopus 로고    scopus 로고
    • SAT-based unbounded symbolic model checking
    • H.-J. Kang and I.-C. Park, "SAT-based unbounded symbolic model checking," IEEE Trans. on CAD, vol. 24, no. 2, pp. 129-140, 2005.
    • (2005) IEEE Trans. on CAD , vol.24 , Issue.2 , pp. 129-140
    • Kang, H.-J.1    Park, I.-C.2
  • 9
    • 0034841433 scopus 로고    scopus 로고
    • Dynamic detection and removal of inactive clauses in SAT with application in image computation
    • A. Gupta, A. Gupta, Z. Yang, and P. Ashar, "Dynamic detection and removal of inactive clauses in SAT with application in image computation," in Design Automation Conf., 2001, pp. 536-541.
    • (2001) Design Automation Conf , pp. 536-541
    • Gupta, A.1    Gupta, A.2    Yang, Z.3    Ashar, P.4
  • 11
    • 0347409201 scopus 로고    scopus 로고
    • SATORI - a fast sequential SAT engine for circuits
    • M. Iyer, G. Parthasarathy, and K. Cheng, "SATORI - a fast sequential SAT engine for circuits." in Int'l Conf. on CAD, 2003, pp. 320-325.
    • (2003) Int'l Conf. on CAD , pp. 320-325
    • Iyer, M.1    Parthasarathy, G.2    Cheng, K.3
  • 14
    • 34547319159 scopus 로고    scopus 로고
    • S. Safarpour, Managing circuit don't cares in Boolean satisfiability, Master's thesis, Department of Electrical and Computer Engineering, Univeristy of Toronto, 2005. [Online]. Available: http://www.eecg.toronto.edu/~sean/thesis.pdf
    • S. Safarpour, "Managing circuit don't cares in Boolean satisfiability," Master's thesis, Department of Electrical and Computer Engineering, Univeristy of Toronto, 2005. [Online]. Available: http://www.eecg.toronto.edu/~sean/thesis.pdf


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.