An approach to the design of PFSCL gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2437-2440

  Alioto, M ^a   Fort, A ^a   Pancioni, L ^a   Rocchi, S ^a   Vignoli, V ^a  

^a UNIVERSITY OF SIENA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESS; DESIGN CRITERION; DESIGN STRATEGIES; NOISE MARGINS; OPTIMUM BALANCE; POWER DISSIPATION; POWER-DELAY TRADEOFF; THEORETICAL RESULT;

ASPECT RATIO;

DESIGN;

EID: 34547238264     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465118     Document Type: Conference Paper

References (11)

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