Implementation of MCML universal logic gate for 10 GHz-range in 0.13 μm CMOS technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Khabiri, Shahnam ^a   Shams, Maitham ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; ENERGY DISSIPATION; LOGIC DESIGN; OPTIMIZATION;

LINEAR MODES; MOS CURRENT MODE LOGIC (MCML); SPECTRE SIMULATOR; SWITCHING NOISE;

LOGIC GATES;

EID: 4344675562     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. Musicer and J. Rabaey, "MOS Current Mode Logic for Low Power, Low Noise CORDIC computations in Mixed-Signal Environments," in ISLPED'OO, pp. 102-107, July 2000.
2. M.W. Allam, M. I. Elmasry, " Dynamic current mode logic (DyMCL): A new low-power high performance logic style," IEEE J. Solid State Circuits, Vol. 36, No. 3, pp. 550-558, March. 2001.
3. Jan Rabaey, "Digital Integrated Circuits: A Design Perspective," Prentice Hall, 1996.
4. M. Alioto, G. Palumbo, S. Pennisi, "Delay estimation of SCL gates with output buffer," in ICECS, Vol. 2, pp. 719-722, Sept. 2001.
5. B. Cochrun, A. Grabel, "A Method for the Determination of the Transfer Function of Electronic Circuits," IEEE Trans. On Circuit Theory, Vol. CT-20, no. 1, pp. 16-20, Jan. 1973.
6. M. Alioto and G. Palumbo,"Modeling propagation delay of MUX, XOR, and D-Latch source coupled logic gates," PATMOS, LNCS 2451,pp. 429-437, 2002.