A new method based on cube algebra for the simplification of logic functions

Arabian Journal for Science and Engineering

Volumn 32, Issue 1 B, 2007, Pages 101-114

  Kahramanli, Şirzat ^a   Güneş, Salih ^a   Şahan, Seral ^a   Başçiftçi, Fatih ^a  

^a SELCUK UNIVERSITY   (Turkey)

Author keywords

Boolean cube; Cube expanding; Direct cover principle; Hypercube; Logic minimization; Logic simplification; Off set based minimization; Prime implicant

Indexed keywords

EID: 34547220469     PISSN: 2193567X     EISSN: 21914281     Source Type: Journal    
DOI: None     Document Type: Article

References (33)

1. T. Sasao, "Worst and Best Irredundant Sum-of-Product Expressions", IEEE Transactions on Computers, 50(9) (2001), pp. 935-947
2. A. Mishchenco and T. Sasao, "Large-Scale SOP minimization Using Decomposition and Functional Properties", DAC 2003, June 2-6, pp. 149-154.
3. P.P. Tirumalai and J.T. Butler, "Minimization Algorithms for Multiple-Valued Programmable Logic Arrays", IEE Transactions on Computers, 40(2) (1991), pp. 167-177.
4. Y. Saad and M.H. Schultz, "Topological Properties of Hypercubes", IEEE Trans. on Comput., C- 37(7) (1988), pp. 867-872.
5. E.W. Veitch, "A Chart Method for Simplifying Truth Functions", Proc. of the ACM, 1952, pp. 127-133.
6. M. Karnaugh, "A Map Method for Synthesis of Combinational Logic Circuits", Trans. AIEE, Comm. and Electronics, 72(1) (1953), pp. 593-599.
7. W.V. Quine, "The Problem of Simplifying Truth Functions", Am. Math. Monthly, 59(8) (1952), pp. 521-531.
8. E. J. McCluskey, "Minimization of Boolean Functions", Bell Systems Tech. J., 35(6) (1956), pp. 1417-1444.
9. M.R. Dagenais, V. K. Agarwal, and N. C. Rumin, "McBoole: A New Procedure for Exact Logic Minimization", IEEE Trans. on Computer-Aided Design, CAD-5(1) (1986), pp. 229-238.
10. R.L. Rudell and A. Sangiovanni-Vincentelli, "Multiple-Valued Minimization for PLA Optimization", IEEE Trans. on Computer-Aided Design, CAD-6(5) (1987), pp. 727-750.
11. R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, "MIS: A Multiple-Level Logic Optimization Systems", IEEE Trans. on Computer-Aided Design, CAD-6(6) (1987), pp. 1062-1081.
12. K. A. Bartlett et al., "Multilevel Logic Minimization Using Implicit Don't Cares", IEEE Trans. on Computer-Aided Design, CAD-7(6) (1988), pp. 723-740.
13. H. Savoj, A.A. Malik, and R.K. Brayton, "Fast Two-Level logic Minimizers for Multi-Level Logic Synthesis", IEEE Int. Conf. on Computer Aided Design, 1989, pp. 426-429.
14. R.K. Brayton and F. Somenzi, "Minimization of Boolean Relations", IEEE Int. Symp. on Circuits and Systems, 1989, pp. 738-743.
15. B. Linn and F. Somenzi, "Minimization of Symbolic Relations", IEEE Int. Conf. on Computer Aided Design, 1990, pp. 88-91.
16. A.A. Malik, R.K. Brayton, A.R. Newton, and A. Sangiovanni-Vincentelli, "Reduced Offset for Two Level Multi-Valued Logic Minimization", IEEE Trans. on Computer-Aided Design, CAD-10(4) (1991), pp. 413-426.
17. M. Pipponzi and F. Somenzi, "An Iterative Algorithm for the Binate Covering Problem", IEEE Trans. on Computer-Aided Design, CAD-10(1) (1991), pp. 208-211.
18. B. Linn, O. Coudert, and J.C. Madre, "Symbolic Prime Generation for Multiple-Valued Functions", 29thACM/IEEE Design Automation Conference, 1992, pp. 40-44.
19. S.W. Jeong and F. Somenzi, "A New Algorithm for the Binate Covering Problem and its Application to the Minimization of Boolean Relations", 29thACM/IEEE Design Automation Conference, 1992, pp. 628-633.
20. P.C. McGeer, J.V. Sanghavi, R.K. Brayton, and A. Sangiovanni-Vincentelli, "ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions", IEEE Trans. on Very Large Scale Integration Systems, VLSI-1(4) (1993), pp. 432-440.
21. T. Kam, T. Villa, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit State Minimization of Nondeterministic FSM's", IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, ICCD '95, 1995, pp. 250-257.
22. C. Legi, B. Wurth, and K. Eckl, "An Implicit Algorithm for Support Minimization During Functional Decomposition", IEEE European Design and Test Conference, 1996, pp. 412-417.
23. T. Kam, T. Villa, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Theory and Algorithms for State Minimization of Nondeterministic FSM's", IEEE Trans. on Computer-Aided Design, CAD-16(11) (1997), pp. 1311-1322.
24. T. Villa, A. Saldanha, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Symbolic Two-Level Minimization", IEEE Trans. on Computer-Aided Design, CAD-16(7) (1997), pp. 692-708.
25. Y. Jiang and R.K. Brayton, "Don't Cares in Logic Minimization of Extended Finite State Machines", IEEE Int. Conf. on Computer Aided Design, 2003, pp. 809-815.
26. E. Nadjafov and. Ş. Kahramanli, "On The Synthesis of Multiple Output Switching Scheme", Scientific Notes of Azerbaijan Institute of Petroleum and Chemistry, 9(3) (1973), pp. 65-69.
27. Ş. Kahramanh, and N. Allahverdi, "An Algebraic Approach to Transformations on Hypercube System", Journal of Mathematical and Computational Applications, 4(1) (1996), pp. 50-59.
28. N. Allahverdi, Ş. Kahramanh, and K. Erciyeş, "A Fault Tolerant Routing Algorithm Based on Cube Algebra for Hypercube System", Journal of System Architecture, Elsevier Science, 46(2) (2000), pp. 201-205.
29. S. Güneş, N. Yilmaz, and N. Allahverdi, "A Fault-Tolerant Multicast Routing Algorithm Based on Cube Algebra for Hypercube Networks", The Arabian Journal for Science and Engineering(AJSE), 28(1B) (2003), pp. 95-103.
30. P. Fišer and J. Hlavička, "BOOM- A Heuristic Boolean Minimizer", Journal of Computing and Informatics, 22 (2003), pp. 1001-1033.
31. S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design. New York: McGraw-Hill, 2003, Ch.4.
32. Ch. Umans, "The Minimum Equivalent DNF Problem and Shortest Implicants", Journal of Computer and System Sciences, 63(2001), pp. 597-611.
33. R. Johnsonbaugh and M. Schaefer, Algorithms. New York: Pearson Prentice Hall, 2004.