Don't cares in logic minimization of extended finite state machines

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 809-815

  Jiang, Yunjian ^a   Brayton, R K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; DIGITAL ARITHMETIC; LOGIC SYNTHESIS; RECONFIGURABLE HARDWARE;

CONTROL AND DATA PATH; DON'T-CARES; EXTENDED FINITE STATE MACHINE; LOGIC MINIMIZATION; MODEL CONTROL; ORIENTED SYSTEMS; PRESBURGER ARITHMETIC; TEST PATTERN GENERATIONS;

LOGIC CIRCUITS;

EID: 84954460326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195129     Document Type: Conference Paper

References (24)

1. T. Amon, G. Borriello, and J. Liu. Making complex timing relationships readable: Presburger formula simplification using don't cares. In Proc. of the Design Automation Conf., June 1998.
2. F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B.Tabbara. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Press, 1997.
3. F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. L. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Trans. Comput.-Aided Design Integrated Circuits, 18(6):834-49, June 1999.
4. G. Berry. A dancing lego mindstorms acrobot programmed in esterel. Technical Report, 2000.
5. G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming, 1992.
6. R. K. Brayton, M. Chiodo, R. Hojati, T. Kam, K. Kodandapani, R. P. Kurshan, S. Malik, A. L. Sangiovanni-Vincentelli, E. M. Sentovich, T. Shiple, K. J. Singh, and H.-Y. Wang. BLIF-MV: An Interchange Format for Design Verification and Synthesis. Technical Report UCB/ERL M91/97, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, Nov. 1991.
7. T. Bultan, R. Gerber, and W. Pugh. Symbolic model checking of infinite state programs using Presburger arithmetic. In Proc. of the Computer-Aided Verification Conf., 1997.
8. 20 states and beyond. In IEEE Symposium on Logic in Computer Science, June 1990.
9. K. T. Cheng and A. Krishnakumar. Automatic functional test generation using the extended finite state machine model. In Proc. of the Design Automation Conf., June 1993.
10. S. Devadas, K. Keutzer, and A. Krishnakumar. Design verification and reachability analysis using algebraic manipulation. In Proc. of the Intl. Conf. on Computer Design, Oct. 1991.
11. H. B. Enderton. A Mathematical Introduction to Logic. Academic Press, 1972.
12. M. Gao, J. Jiang, Y. Jiang, Y. Li, S. Singha, and R. K. Brayton. MVSIS. In Proc. of the Intl. Workshop on Logic Synthesis, May. 2001.
13. V. Glushkov. Automata theory and structural design problems of digital machines. In Cybernetics 1, 1965.
14. S.-Y. Huang. On speeding up extended finite state machines using catalyst circuitry. In Proc. of the Asia and South Pacific Design Automation Conf., Feb. 2001.
15. Y. Jiang and R. K. Brayton. Don't cares and multi-valued logic network minimization. In Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2000.
16. Y. Jiang and R. K. Brayton. Don't care computation in minimizing extended finite state machines with presburger arithmetic. Technical Report UCB/ERL M01/35, Electronics Research Laboratory, University of California, Berkeley, Dec. 2001.
17. Y. Jiang and R. K. Brayton. Software synthesis from synchronous specifications using logic simulation techniques. In Proc. of the Design Automation Conf., June 2002.
18. T. H. Liu, K. Sajid, A. Aziz, and V. Singhal. Optimizing designs containing black boxes. In Proc. of the Design Automation Conf., June 1997.
19. 22pnn upper bound on the complexity of Presburger arithmetic. the Journal of Computer and System Sciences, 1978.
20. M. A. Perkowski and J. E. Brown. Automatic generation of don't cares for the controlling finite state machine from the corresponding behavioral description. In Proc. of the Intl. Symposium on Circuits and Systems, May 1990.
21. W. Pugh and et al. The Omega project, http://www.cs.umd.edu/projects/omega.
22. H. Savoj and R. K. Brayton. The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. In Proc. of the Design Automation Conf., pages 297-301, June 1990.
23. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.
24. T. R. Shiple, J. H. Kukula, and R. K. Ranjan. A comparison of presburger engines for EFSM reachability. In Proc. of the Computer-Aided Verification Conf., 1998.