Heterogeneous multiprocessor implementations for JPEG:: A case study

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 217-222

  Shee, Seng Lin ^a,b   Erdos, Andrea ^a   Parameswaran, Sri ^a,b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b CSIRO   (Australia)

Author keywords

Design; Experimentation; Performance

Indexed keywords

ALGORITHMS; CABLE CORES; COMPUTER SIMULATION; INTELLECTUAL PROPERTY; SYSTEMS ANALYSIS; TRANSISTORS;

JPEG; MASTER-SLAVE MODEL; PIPELINE MODEL; TENSILICA'S XTENSA LX PROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 34547193738     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176307     Document Type: Conference Paper

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