-
1
-
-
0141649587
-
Fermi level pinning at the PolySi/metal oxide interface
-
C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, "Fermi level pinning at the PolySi/metal oxide interface," in VLSI Symp. Tech. Dig., 2003, p. 9.
-
(2003)
VLSI Symp. Tech. Dig
, pp. 9
-
-
Hobbs, C.1
Fonseca, L.2
Dhandapani, V.3
Samavedam, S.4
Taylor, B.5
Grant, J.6
Dip, L.7
Triyoso, D.8
Hegde, R.9
Gilmer, D.10
Garcia, R.11
Roan, D.12
Lovejoy, L.13
Rai, R.14
Hebert, L.15
Tseng, H.16
White, B.17
Tobin, P.18
-
2
-
-
33646875269
-
Gate stack technology for nanoscale devices
-
Jun
-
B. H. Lee, J. Oh, H. H. Tseng, R. Jammy, and H. Huff, "Gate stack technology for nanoscale devices," Mater. Today, vol. 9, no. 6, pp. 32-40, Jun. 2006.
-
(2006)
Mater. Today
, vol.9
, Issue.6
, pp. 32-40
-
-
Lee, B.H.1
Oh, J.2
Tseng, H.H.3
Jammy, R.4
Huff, H.5
-
3
-
-
34447267642
-
High performance dual metal gate CMOS with high mobility and low threshold voltage applicable to bulk CMOS technology
-
S. Yamaguchi, K. Tai, T. Hirano, T. Ando, S. Hiyama, J. Wang, Y. Hagimoto, Y. Nagahama, T. Kato, K. Nagano, M. Yamanaka, S. Terauchi, S. Kanda, R. Yamamoto, Y. Tateshita, Y. Tagawa, H. Iwamoto, M. Saito, N. Nagashima, and S. Kadomura, "High performance dual metal gate CMOS with high mobility and low threshold voltage applicable to bulk CMOS technology," in VLSI Symp. Tech. Dig., 2006, pp. 192-193.
-
(2006)
VLSI Symp. Tech. Dig
, pp. 192-193
-
-
Yamaguchi, S.1
Tai, K.2
Hirano, T.3
Ando, T.4
Hiyama, S.5
Wang, J.6
Hagimoto, Y.7
Nagahama, Y.8
Kato, T.9
Nagano, K.10
Yamanaka, M.11
Terauchi, S.12
Kanda, S.13
Yamamoto, R.14
Tateshita, Y.15
Tagawa, Y.16
Iwamoto, H.17
Saito, M.18
Nagashima, N.19
Kadomura, S.20
more..
-
4
-
-
31744444348
-
Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low power CMOS
-
Y. Shimamoto, J. Yugami, M. Inoue, M. Mizutani, T. Hayashi, K. Shiga, F. Fujita, M. Yoneda, and H. Matsuoka, "Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low power CMOS," in VLSI Symp. Tech. Dig., 2005, pp. 132-133.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 132-133
-
-
Shimamoto, Y.1
Yugami, J.2
Inoue, M.3
Mizutani, M.4
Hayashi, T.5
Shiga, K.6
Fujita, F.7
Yoneda, M.8
Matsuoka, H.9
-
5
-
-
34447279613
-
-
A. Lauwers, A. Veloso, T. Hoffmann, M. J. H. van Dal, C. Vrancken, S. Brus, S. Locorotondo, J.-F. de Marneffe, B. Sijmus, S. Kubicek, T. Chiarella, M. A. Pawlak, K. Opsomer, M. Niwa, R. Mitsuhashi, K. G. Anil, H. Y. Yu, C. Demeurisse, R. Verbeeck, P. Absil, K. Maex, M. Jurczak, S. Biesemans, and J. A. Kittl, CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON, in IEDM Tech. Dig., 2005, pp. 661-664.
-
A. Lauwers, A. Veloso, T. Hoffmann, M. J. H. van Dal, C. Vrancken, S. Brus, S. Locorotondo, J.-F. de Marneffe, B. Sijmus, S. Kubicek, T. Chiarella, M. A. Pawlak, K. Opsomer, M. Niwa, R. Mitsuhashi, K. G. Anil, H. Y. Yu, C. Demeurisse, R. Verbeeck, P. Absil, K. Maex, M. Jurczak, S. Biesemans, and J. A. Kittl, "CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON," in IEDM Tech. Dig., 2005, pp. 661-664.
-
-
-
-
6
-
-
46049115126
-
-
T. Hoffmann, A. Veloso, A. Lauwers, H. Y. Yu, H. Tigelaar, M. Van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, N. Niwa, A. Rothschild, B. Fromnet, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Burns, C. Vrancken, P. P. Absil, M. Jurczak, S. Biesemans, and J. A. Kittl, Ni-based FUSI gates: CMOS Integration for 45 nm node and beyond, in IEDM Tech. Dig., 2006, pp. 10.3.1-10.3.4.
-
T. Hoffmann, A. Veloso, A. Lauwers, H. Y. Yu, H. Tigelaar, M. Van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, N. Niwa, A. Rothschild, B. Fromnet, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Burns, C. Vrancken, P. P. Absil, M. Jurczak, S. Biesemans, and J. A. Kittl, "Ni-based FUSI gates: CMOS Integration for 45 nm node and beyond," in IEDM Tech. Dig., 2006, pp. 10.3.1-10.3.4.
-
-
-
|