Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low-power CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 132-133

  Shimamoto, Y ^a   Yugami, J ^b   Inoue, M ^b   Mizutani, M ^b   Hayashi, T ^b   Shiga, K ^b   Fujita, F ^b   Yoneda, M ^b   Matsuoka, H ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Fermi level pinning; Hf; LOP; LSTP; Work function

Indexed keywords

CMOS INTEGRATED CIRCUITS; FERMI LEVEL; HAFNIUM; IMPURITIES; INTERFACES (MATERIALS); LEAKAGE CURRENTS; MONOLAYERS; THRESHOLD VOLTAGE;

FERMI-LEVEL PINNING; GATE LEAKAGE CURRENT; LOP; WORK-FUNCTION;

GATES (TRANSISTOR);

EID: 31744444348     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469241     Document Type: Conference Paper

References (6)

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4. L. Pantisano et al., VLSI 2004, p. 122.
5. T. Iwamoto et al., IEDM 2003, paper 27.5.
6. T. Watanabe et al., IEDM 2004, paper 20.3.