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Volumn 28, Issue 5, 2007, Pages 681-685

Study on Si-SiGe three-dimensional CMOS integrated circuits

Author keywords

CMOS; Integrated circuits; Si SiGe; Three dimensional

Indexed keywords

SEMICONDUCTING GERMANIUM COMPOUNDS; THREE DIMENSIONAL;

EID: 34347262485     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (8)

References (9)
  • 1
    • 12344311268 scopus 로고    scopus 로고
    • Hole-sheet-density in SiGe pMOS quantum well with δ-doping-layer
    • in Chinese
    • Hu Huiyong, Zhang Heming, Dai Xianying, et al. Hole-sheet-density in SiGe pMOS quantum well with δ-doping-layer. Acta Physica Sinica, 2004, 53(12): 4314(in Chinese).
    • (2004) Acta Physica Sinica , vol.53 , Issue.12 , pp. 4314
    • Hu, H.1    Zhang, H.2    Dai, X.3
  • 2
    • 8844247294 scopus 로고    scopus 로고
    • Junction capacitance models of SiGe HBT
    • in Chinese
    • Lu Yi, Zhang Heming, Dai Xianying, et al. Junction capacitance models of SiGe HBT. Acta Physica Sinica, 2004, 53(9): 3239(in Chinese).
    • (2004) Acta Physica Sinica , vol.53 , Issue.9 , pp. 3239
    • Lu, Y.1    Zhang, H.2    Dai, X.3
  • 3
    • 33746592158 scopus 로고    scopus 로고
    • Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel
    • Jiang Tao, Zhang Heming, Wang Wei, et al. Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel. Chinese Physics, 2006, 15(6): 1339.
    • (2006) Chinese Physics , vol.15 , Issue.6 , pp. 1339
    • Jiang, T.1    Zhang, H.2    Wang, W.3
  • 4
    • 0033699518 scopus 로고    scopus 로고
    • Multiple Si layer ICs: Motivation, performance analysis, and design implications
    • Souri S J, Banerjee K, Methotra A, et al. Multiple Si layer ICs: motivation, performance analysis, and design implications. 37th ACM Design Automation Conf, 2000: 213.
    • (2000) 37th ACM Design Automation Conf , pp. 213
    • Souri, S.J.1    Banerjee, K.2    Methotra, A.3
  • 5
    • 0038104277 scopus 로고    scopus 로고
    • High performance fully-depleted tri-gate CMOS transistors
    • Doyle B S, Datta S, Doczy M, et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett, 2003, 24(4): 263.
    • (2003) IEEE Electron Device Lett , vol.24 , Issue.4 , pp. 263
    • Doyle, B.S.1    Datta, S.2    Doczy, M.3
  • 6
    • 0020830181 scopus 로고
    • Three-dimensional CMOS ICs fabricated by using beam recrystallization
    • Kawamura S, Sasaki N, Iwai T, et al. Three-dimensional CMOS ICs fabricated by using beam recrystallization. IEEE Electron Device Lett, 1983, EDL-4(10): 366.
    • (1983) IEEE Electron Device Lett , vol.EDL-4 , Issue.10 , pp. 366
    • Kawamura, S.1    Sasaki, N.2    Iwai, T.3
  • 7
    • 0035395689 scopus 로고    scopus 로고
    • Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization
    • Chan V W C, Chan P C H, Chan M, et al. Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization. IEEE Trans Electron Devices, 2001, 48(7): 1394.
    • (2001) IEEE Trans Electron Devices , vol.48 , Issue.7 , pp. 1394
    • Chan, V.W.C.1    Chan, P.C.H.2    Chan, M.3
  • 8
    • 0034454104 scopus 로고    scopus 로고
    • Novel silicon epitaxy for advanced MOSFET devices
    • Neudeck G W, Su T C, Denton J P. Novel silicon epitaxy for advanced MOSFET devices. IEEE IEDM, 2000: 169.
    • (2000) IEEE IEDM , pp. 169
    • Neudeck, G.W.1    Su, T.C.2    Denton, J.P.3
  • 9
    • 33646059417 scopus 로고    scopus 로고
    • Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
    • Guarini K W, Topol A W, Ieong M, et al. Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. IEEE IEDM, 2002: 943.
    • (2002) IEEE IEDM , pp. 943
    • Guarini, K.W.1    Topol, A.W.2    Ieong, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.