A 6-Bit 2-GS/s flash aanlog-to-digital converter in 0.18-μm CMOS process

2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Volumn , Issue , 2006, Pages 351-354

  Lin, Ying Zu ^a   Liu, Yen Ting ^a   Chang, Soon Jyh ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; FREQUENCY RESPONSE; OPTIMIZATION; ROM;

CHIP IMPLEMENTATION; COMPARATOR ARRAYS; ENCODERS; SAMPLING RATE;

ANALOG TO DIGITAL CONVERSION;

EID: 34250889447     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2006.357923     Document Type: Conference Paper

References (6)

1. M. Choi and A. Abidi, "A 6-bit 1.3-GSample/s flash ADC in 0.35-μm CMOS," IEEE J. Solid-State Circuits, pp. 1847-1858, Dec. 2001.
2. J. Lee, P. Roux, U.-V. Koc, T. Link, Y. Baeyens, and Y.-K. Chen, "A 5-b 10-GSample/s A/D converter for 10-gb/s optical receivers," IEEE J. Solid-State Circuits, pp. 1671-1679, Oct. 2004.
3. X. Jiang and M. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging," IEEE J. Solid-State Circuits, pp. 532-535, Feb. 2005.
4. P.C.S. Scholtens and et al., "A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE J. Solid-State Circuits, vol. 37, pp. 1599-1609, Dec. 2002.
5. K. Kattmann and J. Barrow, "A technique for reducing differential nonlinearity errors in flash A/D converters," Digest of International Solid-State Circuits Conference, pp. 170-171, Feb. 1991.
6. P.M. Figueiredo and J.C. Vital, "Averaging technique in flash analog-to-digital converters," IEEE Trans Circuit Syts., vol. 51, pp. 233-353, Feb. 2004.