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Volumn 51, Issue 2, 2004, Pages 233-253

Averaging technique in flash analog-to-digital converters

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GAIN MEASUREMENT; MONTE CARLO METHODS; MOSFET DEVICES; TRANSCONDUCTANCE;

EID: 1442312161     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.822415     Document Type: Article
Times cited : (35)

References (17)
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    • Kattmann, K.1    Barrow, J.2
  • 5
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    • Active resistor networks as 2-D sampled data filters
    • Sept
    • J. White and A. Abidi, "Active resistor networks as 2-D sampled data filters," IEEE Trans. Circuits Syst. I, vol. 39, pp. 724-733, Sept. 1992.
    • (1992) IEEE Trans. Circuits Syst. I , vol.39 , pp. 724-733
    • White, J.1    Abidi, A.2
  • 6
    • 0036917305 scopus 로고    scopus 로고
    • A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination
    • Dec
    • P. Scholtens and M. Vertregt, "A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE J. Solid-State Circuits, vol. 37, pp. 1599-1609, Dec. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 1599-1609
    • Scholtens, P.1    Vertregt, M.2
  • 10
    • 0036490574 scopus 로고    scopus 로고
    • Analysis and simulation of distortion in folding and interpolating A/D converters
    • Mar
    • S. Limotyrakis, K. Nam, and B. Wooley, "Analysis and simulation of distortion in folding and interpolating A/D converters," IEEE Trans. Circuits Syst. II, vol. 49, pp. 161-169, Mar. 2002.
    • (2002) IEEE Trans. Circuits Syst. II , vol.49 , pp. 161-169
    • Limotyrakis, S.1    Nam, K.2    Wooley, B.3
  • 11
    • 0037344281 scopus 로고    scopus 로고
    • Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter
    • Mar
    • K. Uyttenhove, J. Vandenbussche, E. Lauwers, G. Gielen, and M. Steyaert, "Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 38, pp. 483-494, Mar. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , pp. 483-494
    • Uyttenhove, K.1    Vandenbussche, J.2    Lauwers, E.3    Gielen, G.4    Steyaert, M.5
  • 14
    • 0035696160 scopus 로고    scopus 로고
    • A6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS
    • Dec
    • M. Choi and A. Abidi, "A6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 1847-1858
    • Choi, M.1    Abidi, A.2
  • 15
    • 84976835846 scopus 로고
    • Numerical inversion of Laplace transforms
    • and 624
    • H. Stehfest, "Numerical inversion of Laplace transforms," Commun. ACM, vol. 13, pp. 47-49 and 624, 1970.
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  • 16
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    • Error analysis of parallel analogue to digital converters
    • May
    • J. Fernandes and M. Silva, "Error analysis of parallel analogue to digital converters," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, May 1994, pp. 341-344.
    • (1994) Proc. IEEE Int. Symp. Circuits and Systems , vol.5 , pp. 341-344
    • Fernandes, J.1    Silva, M.2
  • 17
    • 0028483827 scopus 로고
    • A 25 Ms/s 8-bit CMOS A/D converter for embedded applications
    • Aug
    • M. Pelgrom, A. Rens, M. Vertregt, and M. Dijkstra, "A 25 Ms/s 8-bit CMOS A/D converter for embedded applications," IEEE J. Solid-State Circuits, vol. 29, pp. 879-886, Aug. 1994.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.