A 40-GHz distributed-load static frequency divider

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 205-208

  Lee, Tai Cheng ^a   Lee, Hua Chin ^a   Hsiao, Keng Jan ^a   Huang, Yen Chuan ^a   Chen, Guan Jun ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BROADBAND AMPLIFIERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; LOGIC CIRCUITS;

CURRENT-MODE LOGIC (CML) CIRCUIT; DIFFERENTIAL SIGNAL; WIDEBAND OPERATION;

FREQUENCY DIVIDING CIRCUITS;

EID: 34250754339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251701     Document Type: Conference Paper

References (6)

1. H.-D. Wohlmuth et al., "A high sensitivity static 2:1 frequency divider up to 27 GHz in120nm CMOS," in Proc. Eur. Solid State Circuit Conf. (ESSCIRC), 2002,pp. 823-826.
2. J.-O. Plouchart et al., "A power-efficient 33 GHz 2:1 static frequency divider in 0.12-μm SOI CMOS," in RFIC Symp. Dig. Papers, 2003, pp.329-332.
3. J. Lee and B. Razavi, "A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology," IEEE J. Solid-State Circuits, vol.39, pp.594-601, April 2004.
4. M. Tiebout, "A 50 GHz direct injection locked oscillator topology as low power frequency divider in 0.13 /spl mu/m CMOS," Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European. pp.73-76, Sept. 2003.
5. A. Rylyakov and T. Zwick, "96-GHz Static Frequency Divider in SiGe Bipolar Technology," IEEE J. Solid-State Circuits, vol.39, pp. 1712-1715, Oct. 2004.
6. K. Washio, R. Hayami, E. Ohue, K. Oda, M. Tanabe, H. Shimamoto, and M. Kondo, "67-GHz static frequency divider using 0.2-μm self-aligned SiGe HBTs, " IEEE Trans. Microwave Theory Tech., vol. 49, pp. 3-8, Jan. 2001.