Improving FPGA design robustness with partial TMR

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2006, Pages 226-232

  Pratt, Brian ^a   Caffrey, Michael ^b   Graham, Paul ^b   Morgan, Keith ^a   Wirthlin, Michael ^c  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

^b LOS ALAMOS NATIONAL LABORATORY   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

Error propagation; FPGA; Persistence; Radiation; Selective mitigation; SEU; Simulator; TMR

Indexed keywords

ERROR PROPAGATION; SELECTIVE MITIGATION; TRIPLE MODULAR REDUNDANCY (TMR);

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; ERROR ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); REDUNDANCY; ROBUSTNESS (CONTROL SYSTEMS);

INTEGRATED CIRCUIT LAYOUT;

EID: 34250721630     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2006.251221     Document Type: Conference Paper

References (12)

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10. K. Morgan and M. Wirthlin, "Predicting on-orbit SEU rates", http://dspace.byu.edu, July 2005.
11. "Qpro Virtex 2.5v radiation hardened FPGAs", Tech. Rep., Xilinx Corporation, November 5, 2001, DS028 (v1.2).
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