Diverge-merge processor: Generalized and energy-efficient dynamic predication

IEEE Micro

Volumn 27, Issue 1, 2007, Pages 94-104

  Kim, Hyesoon ^a   Joao, Jose A ^a   Mutlu, Onur ^b   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Adaptivity; Branch prediction; Dynamic predication; Energy efficiency; Instruction level parallelism; Pipelining; Predication

Indexed keywords

ENERGY EFFICIENCY; MULTIPROCESSING PROGRAMS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS;

BRANCH MISPREDICTION PENALTY; DIVERGE-MERGE PROCESSOR; INSTRUCTION LEVEL PARALLELISM;

PROGRAM PROCESSORS;

EID: 34249801218     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.9     Document Type: Article

References (15)

1. O. Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors," Proc. 9th Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 129-140.
2. T.Y. Morad et al., "Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors," Computer Architecture Letters, vol. 4, no. 1, July 2005.
3. J.R. Allen et al., "Conversion of Control Dependence to Data Dependence," Proc. 10th Ann. Symp. Principles of Programming Languages (POPL 83), ACM Press, 1983, pp. 177-189.
4. Y. Choi et al., "The Impact of If-Conversion and Branch Prediction on Program Execution on the Intel Itanium Processor," Proc. 34th Ann. Int'l Symp. Microarchitecture (Micro 01), IEEE CS Press, 2001, pp. 182-191.
5. H. Kim et al., "Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution," Proc. 38th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 05), IEEE CS Press, 2005, pp. 43-54.
6. A. Klauser et al., "Dynamic Hammock Predication for Nonpredicated Instruction Set Architectures," Proc. 7th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 98), IEEE CS Press, 1998, pp. 278-285.
7. H. Kim et al., "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control Flow Graphs Based on Frequently Executed Paths," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 53-64.
8. S.A. Mahlke et al., "Effective Compiler Support for Predicated Execution Using the Hyperblock," Proc. 25th Ann. Int'l Symp. Microarchitecture (Micro 92), IEEE Press, 1992, pp. 45-54.
9. E. Jacobsen, E. Rotenberg, and J. E. Smith, "Assigning Confidence to Conditional Branch Predictions," Proc. 29th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 96), IEEE Press, 1996, pp. 142-152.
10. P.H. Wang et al., "Register Renaming and Scheduling for Dynamic Execution of Predicated Code," Proc. 7th Int'l Symp. High-Performance Computer Architecture (HPCA 01), IEEE CS Press, 2001, pp. 15-26.
11. H. Kim et al., "Profile-Assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors," to be published in Proc. IEEE/ACM Int'l Symp. Code Generation and Optimization (CGO 07), IEEE CS Press, 2007.
12. T. Heil and. J. E. Smith. Selective Dual Path Execution, tech. report, Dept. of Electrical and Computer Engineering, Univ. of Wisconsin-Madison, 1996.
13. A. Klauser, A. Paithankar, and D. Grunwald, "Selective Eager Execution on the Poly-Path Architecture," Proc. 25th Ann. Int'l Symp. Computer Architecture (ISCA 98), IEEE CS Press, 1998, pp. 250-271.
14. S.A. Mahlke et al., "Characterizing to Impact of Predicated Execution on Branch Prediction," Proc. 27th Ann. Int'l Symp. Microarchitecture (Micro 94), IEEE Press, 1994, pp. 217-227.
15. A. Seznec, "Analysis of the O-Geometric History Length Branch Predictor," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA 05), IEEE CS Press, 2005, pp. 394-405.