Materials and device structures for sub-32 nm CMOS nodes

Microelectronic Engineering

Volumn 84, Issue 9-10, 2007, Pages 1845-1852

  Skotnicki, Thomas ^a  

^a STMICROELECTRONICS   (France)

Author keywords

32nm; CMOS; Double gate; Emerging technologies; FDSOI; FinFET; H K gate dielectric; Metallic gate; Mobility; Nano technologies; Power dissipation; Roadmap; Shallow junction; Silicon MOSFET; Silicon on nothing; SRAM; Static noise margin; Strain; Thin body; Thin BOX; Variability

Indexed keywords

ANALOG CIRCUITS; ENERGY DISSIPATION; GATE DIELECTRICS; NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE; STRAIN; TECHNOLOGICAL FORECASTING;

H-K GATE DIELECTRIC; METALLIC GATE; SHALLOW JUNCTION; SILICON MOSFET; STATIC NOISE MARGIN;

CMOS INTEGRATED CIRCUITS;

EID: 34248662701     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.04.091     Document Type: Article

References (14)

1. Skotnicki T., Hutchby J.A., King T.-J., Wong H.-S.P., and Boeuf F. The Road To The End Of Cmos Scaling. IEEE Circuits and Devices Magazine 21 (2005) 16-26
2. T. Skotnicki and F. Boeuf, Optimal scaling methodologies and transistor performance, chapter in "High dielectric constant materials - VLSI MOSFET applications" Edited by H.R. Huff and D. Gilmer, Springer series Microelectronics 16, 2004. MASTAR code is available via http://www.itrs.net/models.html.
3. Jurczak M., Skotnicki T., Paoli M., Tormen B., Martins J., Regolini J.-L., Dutartre D., Ribot P., Lenoble D., Pantel R., and Monfray S. SON (Silicon On Nothing) - an innovative process for advanced CMOS. IEEE TED (2000) 2179-2187
4. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, P. Tobin, Fermi Level Pinning at the PolySi/Metal Oxide Interface, Proc. Symp. VLSI Technology 2003.
5. Bernstein K., et al. High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. & Dev. 50 (2006) 433-449
6. T. Skotnicki, Transistor Scaling to the End of the Roadmap, Proc. Symp. VLSI Technology 2004.
7. T. Skotnicki, Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy?, Proc. ESSDERC 2000, 19-33.
8. Skotnicki T., Merckel G., and Pedron T. The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Letters 9 (1988) 109-112
9. B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, R. Pantel, Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (∼2 Omega/Square) without metal CMP nor etching, IEDM Tech. Dig. 2001, 37.5.1-4.
10. D. Lenoble, Advanced junction fabrication challenges at the 45nm node, pp. 114-130, Semiconductor Fabtech (www.fabtech.org) 30ieth edition, Q2 2006.
11. S. Monfray, T. Skotnicki, B. Tavel, Y. Morand, S. Descombes, A. Talbot, D. Dutartre, C. Jenny, P. Mazoyer, R. Palla, F. Leverd, Y. Le Friec, R. Pantel, M. Haond, C. Charbuillet, C. Vizioz, D. Louis, N. Buffet, SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels, IEDM Tech. Dig. 2002, 263-6.
12. A. Pethe, T. Krishnamohan, K. Donghyun O. Saeroonter, H.-S. Philip Wong, Y. Nishi, K.C. Saraswat, Investigation of performance limits of III-V Double-Gate n-MOSFETs, IEDM Tech. Dig. 2005, 619-622.
13. R.K. Cavin and V. Zhirnov, Future Devices for Information Processing, Proc. ESSDERC 2005, 7-12.
14. H. Iwai, Future semiconductor manufacturing - challenges and opportunities, IEDM Tech. Dig. 2004, 11-16.