Future semiconductor manufacturing - Challenges and opportunities

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 11-16

  Iwai, Hiroshi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; INDUSTRIAL ECONOMICS; INVESTMENTS; LSI CIRCUITS; MOSFET DEVICES; PRODUCTION; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY;

ECONOMIC SOLUTIONS; NANO-DEVICES; PRODUCTION COSTS; TRANSISTOR OPERATIONS;

SEMICONDUCTOR DEVICE MANUFACTURE;

CMOS SCALING; GATE-LENGTH; MANUFACTURING CHALLENGES; MANUFACTURING OPPORTUNITIES; PRODUCTION LEVEL; RESEARCH LEVEL; SEMICONDUCTOR MANUFACTURING; SMALL-GEOMETRY MOSFETS; SUB-100 NM; TRANSISTOR OPERATION;

EID: 21644434450     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. H. Wakabayashi, et al, "Sub-10-nm Planar-Bulk-CMOS Devices using Lateral Junction Control," IEDM Tech., Dig., pp.989 - 991, Washington DC, December, 2003
2. SIA et al., International Technology Roadmap for Semiconductors, 2003 edition.
3. C. Mead and L. Conway, 'Introduction to VLSI systems,' Addison Wesley, p.37, 1979
4. P. P. Gelsinger, "Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers," Dig. Tech. 2001 IEEE International Solid-State Circuits Conference, San Francisco, pp.22-23, February, 2001
5. D. R. Ditzel, "Transmeta's Crusoe: A Low-Power x86-Compatible Microprocessor Built with Software", Proc. Cool Chips III, Tokyo, pp. 1-30, April, 2000.
6. H. Iwai, "CMOS downsizing toward sub-10nm", SolidState Electronics 48,pp497-503, September 2003