Dual-phase line-based QCA memory design

2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

Volumn 1, Issue , 2006, Pages 302-305

  Taskin, Baris ^a   Bo, Hong ^a  

^a Drexel University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; PHASE SHIFT; SYNCHRONIZATION;

ACYCLIC QCA LINES; CLOCK GENERATORS; MEMORY REGIONS;

DATA STORAGE EQUIPMENT;

EID: 34248644544     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nano.2006.247635     Document Type: Conference Paper

References (24)

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