Real-time shape description system based on MPEG-7 descriptors

Journal of Systems Architecture

Volumn 53, Issue 9, 2007, Pages 602-618

  Kapela, Rafał ^a   Rybarczyk, Andrzej ^a  

^a POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

CSD; Dedicated hardware systems; MPEG 7; Real time systems; RSD; Shape recognition

Indexed keywords

APPROXIMATION THEORY; COMPUTATIONAL METHODS; FEATURE EXTRACTION; NEURAL NETWORKS; REAL TIME SYSTEMS;

CURVATURE SCALE SPACE (CSS); DEDICATED HARDWARE SYSTEMS; MPEG-7; SHAPE RECOGNITION;

PATTERN RECOGNITION SYSTEMS;

EID: 34248522578     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2006.12.004     Document Type: Article

References (24)

1. Bebis G., Papadourakis G., and Orphanoudakis S. Curvature scale space driven object recognition with an indexing scheme based on artificial neural networks. Pattern Recognit. 32 7 (1999) 1175-1201
2. T. Ebrahimi, Y. Abdeljaoued, R.M. Figureas, O. Divorra Escoda, MPEG-7 Camera, in: Proceedings of the International Conference on Image Processing, Thessaloniki, vol.3, 2001, pp. 600-603.
3. Chang S.F., Puri A., Sikora T., and Zhang H. Overview of the MPEG-7 Standard. IEEE Trans. Circ. Syst. Video Technol. 11 (2001) 688-695
4. Multimedia content description interface - ISO/IEC 15938-3: 2001, Part 3 Visual, Version 1, 44-52.
5. Fisher W.A., Fujimoto R.J., and Smithson R.C. A programmable analog neural network processor. IEEE Trans. Neural Networks 2 2 (1991) 222-229
6. Fränti P., and Nevalainen O. Compression of binary images by composite methods based on block coding. J. Visual Commun. Image Represent. 6 4 (1995) 366-377 December
7. RC1000 Hardware Reference Manual, Version 2.3, Celoxica Limited, 2001.
8. Gonzalez R.C., and Woods R.E. Digital Image Processing (2002), Prentice-Hall, Inc, Upper Saddle River
9. Guccione S.A., and Gonzalez M.J. A Neural Network Implementation Using Reconfigurable Architectures, More FPGAs, Will Moore and Wayne Luk (1993), Abingdon EE&CS Books, Abingdon, England
10. Hae-Kwang K., and Jong-Deuk K. Region-based shape descriptor invariant to rotation, scale and translation. Signal Process.: Image Commun. 16 1-2 (2000) 87-93 September
11. M. Galindo Hemdndez, R.R. Leal Ascencio, C. Aguilera Galicia, The study of a prototype of an artificial neural network on a field programmable gate array as a function approximator, in: Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, 1999, pp. 126-129.
12. R. Kapela, A. Rybarczyk, The neighboring pixel representation for efficient binary image processing operations, in: Proc. of Parallel Computing in Electrical Engineering, PARELEC, Białystok, Poland, 2006, pp. 396-401.
13. Koenen R., and Pereira F. MPEG-7: A standardised description of audiovisual content. Signal Process.: Image Commun. 16 1-2 (2000) 5-13 September
14. Mokhtarian F., and Mackworth A.K. A theory of multiscale, curvature-based shape representation for planar curves. IEEE Trans. Pattern Anal. Machine Intell. 14 8 (1992) 789-805
15. Manjunath B.S., Salembier P., and Sikora T. Introduction to MPEG-7. Multimedia Content Description Interface (2002), John Wiley and Sons, Ltd
16. Rybarczyk A., and Nowakowski B. A neural network - hardware implementation using FPGA. J. Foundation Comput. Decision Sci. 28 1 (2003) 35-47
17. David Sánchez A.V., Sloat S., Guerrero J., Shullo D., and Lefebvre M. The design of a real-time neurocomputer based on RBF networks. Neurocomputing 20 1-3 (1998) 111-114
18. A. Savakis, P. Śniatała, R. Rudnicki, Real Time Video Annotation Using MPEG-7 Motion Activity Descriptors, in: Proc. Mixed Design of Integrated Circuits and Systems, MIXDES, Łodz, Poland, 1, 2003, pp. 625-628.
19. A. Savakis, P. Śniatała, R. Rudnicki, Hardware Implementation of MPEG-7 Color Descriptors, in: Proc. Mixed Design of Integrated Circuits and Systems, MIXDES, Szczecin, Poland, 1, 2004, pp. 199-203.
20. Shao-Yi C., Bing-Yu H., Yu-Wen H., Shyh-Yih M., and Liang-Gee C. Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems. J. VLSI Signal Process. Syst. Signal, Image, Video Technol. 42 3 (2006) 241-255 March
21. Syeda-Mahmood T., and Petkovic D. On describing color and shape information in images. Signal Process.: Image Commun. 16 1-2 (2000) 15-31 September
22. Rybarczyk A., and Szulc M. The concept of a microcontroller with neural-matrix coprocessor for control systems that exploits reconfigurable FPGAs. ROMOCO, Robot Motion and Control (2002) 123-132
23. Xilinx Product Specification, Dual-Port Block Memory Core v6.3, DS235, 31 August 2005.
24. Xilinx Product Specification, Synchronous FIFO 5.0, DS256, 21 May 2004.