The study of a prototype of an artificial neural network on a field programmable gate array as a function approximator

Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications

Volumn , Issue , 1999, Pages 126-129

  Galindo Hernandez M ^a   Leal Ascencio, R R ^a   Aguilera Galicia, C ^a  

^a Instituto Tecnologico y de Estudios Superiores de Occidente   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

ACCEPTANCE TESTS; COMPUTER PROGRAMMING LANGUAGES; DATA ACQUISITION; INTEGRATED CIRCUITS; MIXED SIGNAL INTEGRATED CIRCUITS; NEURAL NETWORKS; PERSONAL COMPUTERS; SOFTWARE TESTING;

DATA ACQUISITION CARDS; FUNCTION APPROXIMATORS; LABVIEW; TEST BENCHES; TEST CASE; TEST PLAN; TESTING ENVIRONMENT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51649091339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MMICA.1999.833615     Document Type: Conference Paper

References (4)

1. Gschwind M., Salapura V., Maischberger O. "Space efficient neural net implementation". In Proc. Of The Second International ACM/SIGDA Workshop on Field Programmable Gate Arrays, Berkeley, CA, February, 1994.
2. V. Beiu, J. A. Peperstrate, J. Vandewalle and R. Lauwereins, "VLSI Complexity Reduction by Piece -Wise Approximation of the Sigmoid Function", EANN'94, Proceedings of The European Artificial Neural Network Conference, Brussels, Belgium, April, 1994, pp 181-186
3. Holt J.L. and Hwang Jenq-Neng, "Finite precision analysis of neural network hardware implementations" in IEEE Trans on Comp., vol. 42, No. 3, pp 281-290, Mar. 1993.
4. Galindo Hernandez Miriam L., Leal Ascencio R.R. and Aguilera Galicia Cuauhtemoc, "An Artificial Neural Network on a Complex Programmable Logic Device as a Virtual Sensor", Technical Report, DESI, ITESO, Guadalajara, Mexico, January 1998