An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches

Proceedings of the 2006 Workshop on MEmory Performance: DEaling with Applications, Systems and Architectures, MEDEA '06

Volumn 2006, Issue , 2006, Pages 45-52

  Dybdahl, Haakon ^a   Stenström, Per ^b   Natvig, Lasse ^a  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CACHE MEMORY; COMPUTER SIMULATION; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS;

CACHE LINES; CHIP MULTIPROCESSOR SYSTEM; FREQUENCY OF ACCESS; REPLACEMENT ALGORITHM;

ALGORITHMS;

EID: 34248339247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1166133.1166139     Document Type: Article

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