Self-correcting LRU replacement policies

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 181-191

  Kampe, Martin ^a   Stenstrom, Per ^a   Dubois, Michel ^b  

^a Chalmers ^*  (Sweden)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

LRU algorithm; Mistake prediction; Shadow directories

Indexed keywords

ALGORITHMS; BENCHMARKING; DECISION MAKING; ERROR CORRECTION; FEEDBACK; PUBLIC POLICY;

LRU ALGORITHM; MISTAKE PREDICTION; SHADOW DIRECTORIES;

BUFFER STORAGE;

EID: 4143137693     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/977091.977117     Document Type: Conference Paper

References (20)

1. L. A. Barroso, K. Gharachorloo and E. Bugnion. Memory System Characterization of Commercial Workloads. In Proceedings of the 25th International Symposium on Computer Architecture, pp. 3-14, June 1998.
2. L. Belady. A Study of Replacement Algorithms for a Virtual-Storage Computer. In IBM Systems Journal, v. 5, no. 2, pp. 78-103, 1966.
3. D. Burger, Doug and T. M. Austin,. The SimpleScalar . Tool Set, Version 2. University of Wisconsin-Madison Computer Science Department, TN-1342, 1997.
4. A. González, C. Aliagas and M. Valero. A Data Cache with Multiple Caching Strategies tuned to Different Types of Locality. In Proceedings of the 9th ACM international conference on Supercomputing, pp. 338-347, July 1995.
5. J. Jalminger and P. Stenstrom. A Novel Approach to Cache Reuse Prediction. In Proceedings of 32nd International Parallel Processing Conference (ICPP-2003). Oct. 2003.
6. T. L. Johnson, D. A. Connors, M. C. Merten, and W. W. Hwu. Run-Time Cache Bypassing. In IEEE Transactions on Computers, Vol. 48, No. 12, pp. 1338-1354, December 1999.
7. T. L. Johnson and W. Hwu. Run-time Adaptive Cache Hierarchy Management via Reference Analysis. In Pro ceedings of the 24th International Symposium on Computer Architecture, pp. 315-326, June 1997.
8. N.P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associativ Cache and Prefetch Buffers. In Proceedings of the 17th International Symposium on Computer Architecture, pp. 364-373, May 1990.
9. M. Karlsson and E. Hagersten, "Timestamp-based Selective Cache Allocation", High Performance Memory Systems, edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, Springer-Verlag, 2003.
10. M. Kämpe and F. Dahlgren. Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. In Proceedings of the 14th International Parallel and Distributed Computing Symposium, pp. 163-170, May 2000
11. A-C Lai, C. Fide, and B. Falsafi. Dead-block Prediction and Dead-block Correlating Prefetchers. In Proceedings of the 28th International Symposium on Computer Architecture, pp. 144-154, July 2001.
12. R. L. Mattson, J. Gecsei, D. R. Slutz and I. L. Traiger. Evaluation Techniques for Storage Hierarchies. In IBM Systems Journal, vol. 9, pp. 77-117, 1970.
13. V. Milutinovic, B. Markovic, M. Tomasevic, and M. Tremblay. The Split Temporal/Spatial Cache: Initial Performance analysis. In Proceedings of SCIzzL-5, pp. 63-70, March 1996.
14. M. Prvulovic, D. Marinov, Z. Dimitrijevic, and V. Milutinovic. Split Temporal/Spatial Cache: A Survey and Reevaluation of Performance, IEEE TCCA Newsletter, pp. 1-10, 1999.
15. A. J. Smith. Cache Memories. ACM Computing Surveys, vol. 3, pp. 473-530, September 1982.
16. Standard Performance Evaluation Corporation, http://www.spec.org. SPEC 95. August 1995.
17. H. S. Stone. High Performance Computer Architecture. Addison-Wesley 1993 (3rd ed.).
18. E. S. Tam, J.A. Rivers, V. Srinivasan, G.S. Tyson, and E.S. Davidson. Active Management of Data Caches by Exploiting Reuse Information. In IEEE Transactions on Computers, Vol. 48, No. 11, pp. 1244-1259, November 1999.
19. Gary Tyson, Matthew Farrens, John Matthews, Andrew R Pleszkun. A Modified Approach to Data Cache Management. In Proceedings of MICRO-28, pp. 93-103, November 1995.
20. Wayne A. Wong and Jean-Loup Baer. Modified LRU Policies for Improving Second-level Cache Behavior. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, pp. 49-60, January 2000.