Hybrid nanocrystal FinFET with large P/E window for MLC NAND Flash memory application

Electronics Letters

Volumn 43, Issue 9, 2007, Pages 545-546

  Choe, J D ^a   Ahn, Y J ^a   Lee, S H ^a   Jang, D ^a   Yoon, Y B ^a   Lee, J J ^a   Chung, I ^b   Park, K ^a   Park, D ^a  

^a SAMSUNG Electronics   (South Korea)

^b Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TRAPS; FLASH MEMORY; NAND CIRCUITS; NANOCRYSTALLINE MATERIALS;

NANOCRYSTAL TRAP LAYERS; TRAP DENSITY;

FIELD EFFECT TRANSISTORS;

EID: 34247611926     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20070605     Document Type: Article

References (5)

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3. Coffin, H., Bonafos, C., Schamm, S., Carrada, M., Cherkashin, N., Assayag, G.B., Dimitrakis, P., Normand, P., Respaud, M., and Claverie, A.: 'Si nanocrystals by ultra-low energy ion implantation for non-volatile memory applications', Mater. Sci. Eng., 2005, B124-125, pp. 499-503
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5. Lu, T.Z., Alexe, M., Scholz, R., Talelaev, V., and Zacharias, M.: 'Multilevel charge storage in silicon nanocrystal multilayers', Appl. Phys. Lett., 2005, 87, p. 202110