VICTORIA - VMX indirect compute technology oriented towards in-line acceleration

Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06

Volumn 2006, Issue , 2006, Pages 303-311

  Derby, Jeff H ^a   Montoye, Robert K ^b   Moreira, José ^b  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Accelerators; PowerPC; SIMD; VMX

Indexed keywords

MEMORY LATENCY; REGISTER ADDRESSING; VECTOR ALGORITHMS;

CODES (SYMBOLS); COMPUTER ARCHITECTURE; OPTIMIZATION; PROGRAM PROCESSORS; VECTORS;

COMPUTER SYSTEMS;

EID: 34247387642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1128022.1128062     Document Type: Conference Paper

References (14)

1. IBM Corporation. PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual. Ver. 2.06, 22 Aug. 2005.
2. Intel Corporation. Intel* Itanium® Architecture Software Developer's Manual, Vol. 2: System Architecture. Oct. 2002.
3. http://www-128.ibm.com/developerworks/power/library/pa-cellperf/.
4. Tyson, G. S., Smelyanskiy, M., and Davidson, E. S. Evaluating the use of register queues in software pipelined loops. IEEE Trans. Comput., vol. 50 no. 8 (Aug. 2001), 769-783.
5. th Annual International Symposium on Computer Architecture (ISCA'20) (San Diego, CA, May 16-19, 1993). 247-256.
6. Moreno, J. H., et. al. An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Devel., vol. 47 no. 2/3 (March/May 2003), 299-326.
7. Cascaval, C. G. and Chatterjee, S. System and Method for Encoding and Decoding Architecture Registers. US Pat. Appl. 20050060520, 17 Mar. 2005.
8. Quintana, F., Corbal, J., Espasa, R., Valero, M. Adding a vector unit to a superscalar processor. In Proc. 13th International Conference on Supercomputing (Rhodes, Greece, June 20 - 25, 1999), 1-10.
9. th Annual International Symposium on Computer Architecture (Anchorage, AK, May 25-29, 2002). 281-292.
10. Kozyrakis, C. and Patterson,D. Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks. In Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-35) (Istanbul, Turkey, Nov. 18-22, 2002). 283-293.
11. Jouppi, N. P., Bertoni, J., and Wall, D. W. A unified vector/scalar floating architecture. In Proc. ASPLOS-III: the Third International Conference on Architecture Support for Programming Languages and Operating Systems (April 1989). 134-143.
12. Chang, L., et. al. Stable SRAM cell design for the 32 nm node and beyond. In 2005 Symp. VLSI Tech. Dig. Of Tech. Papers (Kyoto, Japan, Jun. 2005). 128-129.
13. Derby, J. H. and Moreno, J. H. A high-performance embedded DSP with novel SIMD features. In Proc. ICASSP'03 (Hong Kong, Apr. 6 -10, 2003), II - 301-304.
14. Naishlos, D., Biberstein, M., Ben-David, S., and Zaks, A. Vectorizing for a SIMdD DSP architecture. In Proc. CASES'03 (San Jose, CA, Oct. 2003).