Vectorizing for a SIMdD DSP architecture

CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2003, Pages 2-11

  Naishlos, Dorit ^a   Biberstein, Marina ^a   Ben David, Shay ^a   Zaks, Ayal ^a  

^a UNIVERSITY OF HAIFA   (Israel)

Author keywords

Compiler controlled cache; Data reuse; Rotating register file; SIMD; Subword parallelism; Vectorization; Viterbi

Indexed keywords

CACHE MEMORY; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DECODING; DIGITAL SIGNAL PROCESSING; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM COMPILERS; VECTORS;

COMPILER CONTROLLED CACHE; DATA ELEMENTS; SINGLE INSTRUCTION MULTIPLE DATA (SIMD); VECTORIZATION;

DATA STRUCTURES;

EID: 4544372264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/951710.951714     Document Type: Conference Paper

References (23)

1. K. Asanovic and D. Johnson. Torrent architecture manual. Technical report, ICSI, 1996.
2. A. J. C. Bik, M. Girkar, P. M. Grey, and X. Tian. Efficient exploitation of parallelism on Pentium III and Pentium 4 processor-based systems. Intel Technology J., February 2001.
3. David Callahan, S. Carr, and K. Kennedy. Improving register allocation for subscripted variables. In PLDI, pages 53-65, June 1990.
4. William Y. Chen, R. Bringmann, S. A. Mahlke, R. E. Hank, and J. E. Sicolo. An efficient architecture for loop based data preloading. In Micro, 1992.
5. Keith Cooper, Ken Kennedy, and Nathaniel McIntosh. Cross-loop reuse analysis and its application to cache optimizations. In Ninth Workshop on Languages and Compilers for Parallel Computing, August 1996.
6. Jesus Corbal, Roger Espasa, and Mateo Valero. Exploiting a new level of DLP in multimedia applications. In Intl. Symposium on Microarchitecture, pages 72-, 1999.
7. Paul D'Arcy and Scott Beach. StarCore SC140: A new DSP architecture for portable devices. In Wireless Symposium. Motorola, September 1999.
8. K. Diefendorff and P. K. Dubey et al. Altivec extension to PowerPC accelerates media processing. IEEE Micro, March-April 2000.
9. Gautam Dohsi, Rakesh Krishnaiyer, and Kalyan Muthukumar. Optimizing software data prefetches with rotating registers. In PACT, pages 257-267, 2001.
10. Texas Instruments, www.ti.com/sc/c6x, 2000.
11. M. Kandemir, I. Kadayif, A. Choudhary, and J. A. Zambreno. Optimizing inter-nest data locality. In PACT, pages 127-135, 2002.
12. Andreas Krall and Sylvain Lelait. Compilation techniques for multimedia processors. Intl. J. of Parallel Programming, 28(4):347-361, 2000.
13. Samuel Larsen, Emmett Witchel, and Saman Amarasinghe. Techniques for increasing and detecting memory alignment. Technical Memo 621, MIT LCS, November 2001.
14. J. H. Moreno, M. Moudgill, K. Ebcioglu, E. Altman, B. Hall, R. Miranda, S. K. Chen, and A. Polyak. Simulation/evaluation environment for a VLIW processor architecture. IBM Journal of Research and Development, 41(3):287-302, May 1997.
15. Jaime H. Moreno, V. Zyuban, U. Shvadron, F. Neeser, J. Derby, M. Ware, K. Kailas, A. Zaks, A. Geva, S. Ben-David, S. Asaad, T. Fox, M. Biberstein, D. Naishlos, and H. Hunter. An innovative low-power high-performance programmable signal processor for digital communications. IBM Journal of Research and Development, March 2003.
16. Steven S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
17. Huy Nguyen and Lizy Kurian John. Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology. In Intl. Conf., on Supercomputing, pages 11-20, 1999.
18. Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau. Efficient utilization of scratch-pad memory in embedded processor applications. In European Design and Test Conf., March 1997.
19. A. Peleg and U. Weiser. MMX technology extension to the Intel architecture. IEEE Micro, pages 43-45, August 1996.
20. K. Pingali, M. Beck, R. Johnson, M. Moudgill, and P. Stodghill. Dependence flow graphs: an algebraic approach to program dependencies. In POPL, pages 67-78, 1991.
21. Matthew Postiff. Compiler and Microarchitecture Mechanisms for Exploiting Registers to Improve Memory Performance. PhD thesis, U. of Michigan, 2001.
22. Jaewook Shin, Jacqueline Chame, and Mary W. Hall. Compiler-controlled caching in superword register files for multimedia extension architectures. In PACT, 2002.
23. Michael Wolfe. High Performance Compilers for Parallel Computing. Addison Wesley, 1996.