Practical evaluation of fault countermeasures on an asynchronous DES crypto processor

Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium

Volumn 2006, Issue , 2006, Pages 125-130

  Monnet, Y ^a   Renaudin, M ^a   Leveugle, R ^a   Feyt, N ^b   Moitrel, P ^b   Nzenguet, F M'Buwa ^b  

^a TIMA LABORATORY   (France)

^b GEMPLUS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS MACHINERY; CMOS INTEGRATED CIRCUITS; FAILURE ANALYSIS; MICROELECTRONICS;

ASYNCHRONOUS DES COPROCESSOR; CRYPTO PROCESSORS; FAULT INJECTION; LOGIC BLOCKS;

CRYPTOGRAPHY;

EID: 34247219213     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2006.50     Document Type: Conference Paper

References (7)

1. H. Bar-El, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan. The sorcerers apprentice guide to fault attacks. Workshop on Fault Diagnosis an Tolerance in Cryptography, in association with DSN 2004, The International Conference on Dependable Systems and Networks, June 2004.
2. V. Pouget. "Simulation expérimentale par impulsions laser ultra-courtes des effets des radiations ionisantes sur les circuits intégrés", Thèse de doctorat de l'Université de Bordeaux I, 2000
3. Y. Monnet, M. Renaudin, R. Leveugle, "Hardening Techniques against Transient Faults for Asynchronous Circuits", 11th IEEE International Qn-Line Testing Symposium (IOLTS), Saint Raphael, French Riviera, France, July 6th-8th, 2005, pp. 129-134.
4. Y. Monnet, M. Renaudin, R. Leveugle, S. Dumont, F. Bouesse, "An Asynchronous DES Crypto-Processor Secured against Fault Attacks", International Conference on Very Large Scale Integration (VLSI-SOC), 2005, pp. 21-26.
5. M. Renaudin, "Asynchronous Circuits and Systems: a promising design alternative", Microelectronics-Engineering Journal, Elsevier Science, Guest Editors: P.Senn, M. Renaudin, J. Boussey, Vol54, No1-2, December 2000, pp. 133-149.
6. S. Moore, R. Anderson, R. Mullins, G. Taylor, J. J. A. Fournier, "Balanced self-checking asynchronous logic for smart card applications", Microprocessors and Microsystems, Elsevier Science Publishers, vol. 27, 2003, pp. 421-430.
7. NIST, Data Encryption Standard (DES), FIPS PUB 46-2, National Institute of Standards and Technology,http://csrc.nist.gov/csrc/fedstandards.html