2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LAN's and WAN's

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 6, 1999, Pages 805-812

  Kishine, Keiji ^a,b,c   Ishihara, Noboru ^b,d   Takiguchi, Ken Ichi ^b,e   Ichino, Haruhiko ^a,b,f  

^a NTT Network Innovation Laboratories   (Japan)

^b NTT CORPORATION   (Japan)

^c KYOTO UNIVERSITY   (Japan)

^d TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^e Tokyo Medical University   (Japan)

^f OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; GAIN CONTROL; LOCAL AREA NETWORKS; OPTIMIZATION; SEMICONDUCTING SILICON; SIGNAL RECEIVERS; SPECIFICATIONS; SPURIOUS SIGNAL NOISE; SWITCHED FILTERS; TIMING CIRCUITS; WIDE AREA NETWORKS;

CLOCK AND DATA RECOVERY INTEGRATED CIRCUIT; JITTER SUPPRESSION; POWER CONSUMPTION; TRANSMISSION RECEIVER;

PHASE LOCKED LOOPS;

EID: 0032661534     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766814     Document Type: Article

References (7)

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