Top-down design of a low-power multi-channel 2.5-Gbit/s/channel gated oscillator clock-recovery circuit

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 258-263

  Muller, Paul ^a   Tajalli, Armin ^b   Atarodi, Mojtaba ^b   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

^b SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; OSCILLATORS (ELECTRONIC); STATISTICAL METHODS; THERMAL NOISE; TOPOLOGY;

BLOCK CONSTRAINTS; CLOCK RECOVERY CIRCUIT; STATISTICAL SIMULATION; THERMAL NOISE MODELING;

GATEWAYS (COMPUTER NETWORKS);

EID: 33646907143     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.315     Document Type: Conference Paper

References (8)

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