Detailed comparisons of program, erase and data retention characteristics between P+-and N+-poly SONOS NAND flash memory

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2006, Issue , 2006, Pages 77-79

  Kuo, Victor Chao Wei ^a   Chao, Chih Ming ^a   Kang, Chih Kai ^a   Liu, Li Wei ^a   Huang, Tzung Bin ^a   Kuo, Liang Tai ^a   Chen, Shi Hsien ^a   Wei, Houng Chi ^a   Hwang, Hann Ping ^a   Pittikoun, Saysamone ^a  

^a POWERCHIP TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; ELECTRON TRAPS; FUNCTIONS; GATES (TRANSISTOR); NONVOLATILE STORAGE; THERMAL EFFECTS;

DATA RETENTION; NAND FLASH MEMORY; POLY GATES; SONOS;

FLASH MEMORY;

EID: 34047223867     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2006.10     Document Type: Conference Paper

References (6)

1. J. D. Lee et al., "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation," IEEE Electron Device Letters, vol. 23, no. 5, May 2002, pp. 264-266.
2. K. Kim et al., "Future Memory Technology including Emerging New Memories," International Conference on Micro-electronics, May 2004, pp.377-384.
3. C. H. Lee et al., "A novel SONOS structure of SiO/sub 2//SiN/Al/sub 2/O/sub 3/with TaN metal gate for multi-giga bit flash memories," IEEE Electron Devices Meeting, Dec. 2003, pp.26.5.1-26.5.4.
4. H. Reisinger et al., "A Novel SONOS Structure for Nonvolatile Memories with Improved Data Retention," VLSI Technology Digest, 1997, pp. 113-114.
5. Y. Wang et al., "An Analytical Retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State," IEEE.
6. S. S. Chung et al., "A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell," IEEE Electron Devices Meeting, Dec. 2003, pp.26.6.1-26.6.4.