Performance evaluation for system-on-chip architectures using trace-based transaction level simulation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Wild, T ^a   Herkersdorf, A ^a   Ohlendorf, R ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; INTEGRATED CIRCUITS; RESOURCE ALLOCATION; SYSTEMS ANALYSIS;

SYSTEM ARCHITECTURE; SYSTEM-ON-CHIP (SOC) ARCHITECTURES; TRANSACTION LEVEL SIMULATION;

COMPUTER ARCHITECTURE;

EID: 34047183206     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244111     Document Type: Conference Paper

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