Low power synthesis of dynamic logic circuits using fine-grained clock gating

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Banerjee, Nilanjan ^a   Roy, Kaushik ^a   Mahmoodi, Hamid ^b   Bhunia, Swarup ^c  

^a PURDUE UNIVERSITY   (United States)

^b SAN FRANCISCO STATE UNIVERSITY   (United States)

^c CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DELAY CIRCUITS; ELECTRIC POWER UTILIZATION; SYSTEMS ANALYSIS;

BENCHMARK CIRCUITS; CLOCK GATING; CLOCK POWER; DYNAMIC LOGIC CIRCUITS; SKEWED LOGIC;

LOGIC CIRCUITS;

EID: 34047182643     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243769     Document Type: Conference Paper

References (11)

1. nd Edition, Prentice Hall.
2. A. Solomatnikov et al., Skewed CMOS: noise-tolerant high-performance low-power static circuit family, IEEE TVLSI, Vol. 10, pp. 469-476, 2002.
3. A. Cao et al., Synthesis of skewed logic circuits, ACM TODAES, Vol. 10, pp. 205-228, 2004.
4. H. Li et al., DCG; Deterministic clock-gating for low-power microprocessor design, IEEE TVLSI, Vol. 12, pp. 245-254, 2004.
5. P. Babighian et al., A scalable algorithm for RTL insertion of gated clocks based on ODCs computation, IEEE TCAD, Vol. 24, pp. 29-42, 2005.
6. R. Krishnamurthy et al., High-performance and low-power challenges for sub-70 nm microprocessor circuits, CICC, pp. 12-15, 2002.
7. A. Chandrakasan, Design of High-Performancc Microprocessor Circuits, IEEE Press.
8. S. Bhunia et al., A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating, DAC, pp. 479-484, 2005.
9. L. Lavagno et al., Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool, DAC, pp. 254-260, 1995.
10. Zhao et al., Technology Mapping Algorithms for domino logic, ACM TODAES, Vol. 7, pp. 306-335, 2002.
11. SIS, University of California at Berkeley.