Simultaneous scheduling, binding and floorplanning in high-level synthesis

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 428-434

  Prabhakaran, Pradeep ^a   Banerjee, Prithviraj ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MATHEMATICAL MODELS; SIMULATED ANNEALING;

FLOORPLANNING ALGORITHMS; HIGH LEVEL SYNTHESIS; INTERCONNECT DELAYS;

LOGIC DESIGN;

EID: 0031651853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)