A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006

Volumn 2006, Issue , 2006, Pages

  Liu, Zhenyu ^a   Song, Yang ^b   Ikenaga, Takeshi ^b   Goto, Satoshi ^b  

^a Kitakyushu Foundation for the Advancement of Industry   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

H.264 AVC; Variable block size motion estimation; VLSI architecture

Indexed keywords

COMPUTER HARDWARE; IMAGE CODING; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

H.264/AVC; PROCESS ELEMENT GROUP (PEG); PROCESS ELEMENTS (PE); VARIABLE BLOCK SIZE MOTION ESTIMATION (VBSME);

PIPELINE PROCESSING SYSTEMS;

EID: 34047130694     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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6. C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C.Wang and L. G. Chen, "Analysis and architectrue design of variable block size motion estimation for H.264/AVC", IEEE Transactions on Circuits and Systems-I: Regular Papers (in press).