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Volumn , Issue , 2006, Pages 1945-1948

On-chip and inter-chip networks for modelling large-scale neural systems

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; LARGE SCALE SYSTEMS; MULTICASTING; NEURAL NETWORKS;

EID: 34047120637     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (33)

References (10)
  • 1
    • 34547240352 scopus 로고    scopus 로고
    • K. Asanovic, J. Beck, T. Callahan, J. Feldman, B.S. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire & J. Wawrzynek, CNS-I Architecture Specification, EECS Department, UC Berkeley, Technical Report No. UCB/CSD-93-747, 1993.
    • K. Asanovic, J. Beck, T. Callahan, J. Feldman, B.S. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire & J. Wawrzynek, CNS-I Architecture Specification, EECS Department, UC Berkeley, Technical Report No. UCB/CSD-93-747, 1993.
  • 2
    • 33744526665 scopus 로고    scopus 로고
    • MASPINN: Novel Conoepts for a NeuroAccelerator for Spiking Neural Networks
    • Stockholm, June 22-26
    • T. Schoenauer, N. Mehrtash, A. Jahnke & H. Klar, "MASPINN: Novel Conoepts for a NeuroAccelerator for Spiking Neural Networks", Proc. VIDYNN'98, Stockholm, June 22-26, 1998.
    • (1998) Proc. VIDYNN'98
    • Schoenauer, T.1    Mehrtash, N.2    Jahnke, A.3    Klar, H.4
  • 4
    • 4344661328 scopus 로고    scopus 로고
    • Which Model to Use for Cortical Spiking Neurons?
    • E.M. Izhikevich, "Which Model to Use for Cortical Spiking Neurons?", IEEE Trans. Neural Networks 15, 2004, pp. 1063-1070.
    • (2004) IEEE Trans. Neural Networks , vol.15 , pp. 1063-1070
    • Izhikevich, E.M.1
  • 5
    • 8444226339 scopus 로고    scopus 로고
    • A Sparse Distributed Memory based upon N-of-M Codes
    • December
    • S.B. Furber, W.J. Bainbridge, J.M. Cumpstey and S. Temple, "A Sparse Distributed Memory based upon N-of-M Codes", Neural Networks 17(10), December 2004, pp. 1437-1451.
    • (2004) Neural Networks , vol.17 , Issue.10 , pp. 1437-1451
    • Furber, S.B.1    Bainbridge, W.J.2    Cumpstey, J.M.3    Temple, S.4
  • 6
    • 0036761283 scopus 로고    scopus 로고
    • CHAIN: A Delay-Insensitive Chip Area Interconnect
    • special issue on the Design and Test of System-on-Chip , September/October
    • W.J. Bainbridge and S.B. Furber, "CHAIN: A Delay-Insensitive Chip Area Interconnect", IEEE Micro, special issue on the Design and Test of System-on-Chip 22(5), September/October 2002, pp. 16-23.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 16-23
    • Bainbridge, W.J.1    Furber, S.B.2
  • 7
    • 34547300106 scopus 로고    scopus 로고
    • http://www.silistix.com
  • 8
    • 3042515271 scopus 로고    scopus 로고
    • The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip
    • Paris, Feb
    • W.J. Bainbridge, L.A. Plana & S.B. Furber, "The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip", Proc. DATE'04, Vol. 3, Paris, Feb 2004, p. 274.
    • (2004) Proc. DATE'04 , vol.3 , pp. 274
    • Bainbridge, W.J.1    Plana, L.A.2    Furber, S.B.3
  • 9
    • 77957960152 scopus 로고    scopus 로고
    • Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes
    • Vancouver, May
    • W.J. Bainbridge, W.B. Toms, D.A. Edwards, S.B. Furber, "Delay-Insensitive, Point-to-Point Interconnect using m-of-n codes", Proc. Async '03, Vancouver, May 2003, pp. 132-140.
    • (2003) Proc. Async '03 , pp. 132-140
    • Bainbridge, W.J.1    Toms, W.B.2    Edwards, D.A.3    Furber, S.B.4
  • 10
    • 34547329025 scopus 로고    scopus 로고
    • http://www.arm.com/products/CPUs/ARM968E-S.html


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.