Timing-driven cell layout De-compaction for yield optimization by critical area minimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Iizuka, Tetsuya ^a   Ikeda, Makoto ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; OPTIMIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

CELL LAYOUT; CRITICAL AREA MINIMIZATION;

LOGIC CIRCUITS;

EID: 34047113966     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243774     Document Type: Conference Paper

References (5)

1. A. Nardi and A. L. Sangiovanni-Vincentelli, "Synthesis for Manufacturability: a Sanity Check," in Proc. IEEE/ACM Design, Automation and Test in Europe, pp. 796-801, 2004.
2. C. Guardiani, N. Dragone, and P. McNamara, "Proactive Design For Manufacturability (DFM) for Nanometer SoC Designs," in Proc. IEEE Custom Integrated Circuits Conf., pp. 15.1.1-15.1.8, 2004.
3. C. Bamji and E. Malavasi, "Enhanced Network Flow Algorithm for Yield Optimization," in Proc. ACM/IEEE 33rd Design Automation Conference, pp. 746-751, 1996.
4. Y. Bourai and C.-J. R. Shi, "Layout Compaction for Yield Optimization via Critical Area Minimization," in Proc. IEEE/ACM Design, Automation and Test in Europe, pp. 122-125, 2000.
5. X. Yuan, K. W. McCullen, F.-L. Heng, R. F. Walker, J. Hibbeler, R. J. Allen, and R. R. Narayan, "Technology Migration Technique for Designs with Strong RET-Driven Layout Restrictions," in Proc. ACM Int. Symp. on Physical Design, pp. 175-182, 2005.