A configurable enhanced TTRAM macro for system-level power management unified memory

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 853-861

  Morishita, Fukashi ^b   Hayashi, Isamu ^b   Gyohten, Takayuki ^b   Noda, Hideyuki ^a   Ipposhi, Takashi ^a   Shimano, Hiroki ^a   Dosaka, Katsumi ^a   Arimoto, Kazutami ^a,b  

^a IEEE

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Capacitorless DRAM; Power management; SOI; System on chip; Unified memory

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER MEASUREMENT; MICROPROCESSOR CHIPS; TRANSISTORS; VOLTAGE CONTROL;

CAPACITORLESS DRAM; SYSTEM-ON-CHIP; UNIFIED MEMORY; VOLTAGE ARRAYS;

RANDOM ACCESS STORAGE;

EID: 33947696724     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.891677     Document Type: Article

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